參數(shù)資料
型號: L64007
廠商: LSI CORP
元件分類: 消費家電
英文描述: SPECIALTY CONSUMER CIRCUIT, PQFP160
封裝: PLASTIC, QFP-160
文件頁數(shù): 122/166頁
文件大小: 1015K
代理商: L64007
Arch
51 Wed May 28 17:36:23 1997
Draft 1/21/97
L64007 MPEG-2, DVB, JSAT Transport Demultiplexer Technical Manual
2-51
PRE.4 for Rev. D
Copyright 1997 by LSI Logic Corporation. All rights reserved.
The host processor interface supports data transfer operations from the
host bus to an external DRAM device through the L64007. Data can be
transferred using either a direct access mechanism or an external DMA
controller service.
DRAM access is done using an on-chip Cache memory. The Cache
allows better utilization of the DRAM controller’s fast page mode mech-
anism by serving as a fast memory buffer for the host. From the host pro-
cessor bus, the interface to the DRAM memory is done through the
Cache memory. When there is a Cache hit, data is available immediately.
When there is a Cache miss, the data is available to the host after the
DRAM controller transfers the line containing the missing word into the
Cache memory. Figure 2.46 shows the concept of DRAM access through
the L64007 using the Cache memory and Cache controller.
A[19:0]
R/W
AS
CS
D[15:8]
DTACK
Latch Address
End of Write Bus Cycle
End
Start
Write
UDS
LDS
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