Draft 1/16/97
L64007 MPEG-2, DVB, JSAT Transport Demultiplexer Technical Manual
3-9
PRE.4 for Rev. D
Copyright 1997 by LSI Logic Corporation. All rights reserved.
3.9
DRAM Interface
BA[9:0]
Buffer Address Bus
On a HIGH-to-LOW transition of the RAS signal, this out-
put address bus to external DRAM memory holds the row
address. On the HIGH-to-LOW transition of CAS, this bus
holds the column address.
BD[15:0]
Buffer Data Bus
Bidirectional
This bidirectional 16-bit data bus transfers data to and
from the external buffer memory.
BOE
Buffer Output Enable
Output
This active LOW output signal enables the DRAM device
to drive the BD[15:0] data bus during a read cycle.
BWE
Buffer Write Enable
Output
This active LOW output signal indicates write cycles to
the external DRAM device. When LOW, it causes data on
BD[15:0] to be written into DRAM on the HIGH-to-LOW
transition of the CASH and CASL signals.
CASH
Column Address High Strobe
Output
This active LOW output signal to external DRAM device
latches the column address on BA[9:0] lines on the
HIGH-to-LOW transition of the CASH signal. CASH indi-
cates that the actual access of this 16-bit DRAM bus
transaction is intended for the high-byte memory, which
is attached to BD[15:8].
CASL
Column Address Low Strobe
Output
This active LOW output signal to external DRAM device
latches the column address on BA[9:0] on the HIGH-to-
LOW transition of the CASL signal. CASL indicates that
the actual access of this 16-bit DRAM bus transaction is
intended for the low-byte memory, which is attached to
BD[7:0]
RAS
Row Address Strobe
Output
This active LOW output signal to external DRAM device
latches the row address on BA[9:0] on the HIGH-to-LOW
transition.