參數(shù)資料
型號： L64007
廠商： LSI CORP
元件分類： 消費家電
英文描述： SPECIALTY CONSUMER CIRCUIT, PQFP160
封裝： PLASTIC, QFP-160
文件頁數(shù)： 159/166頁
文件大小： 1015K
代理商： L64007
register
10 Wed May 28 17:37:25 1997
Draft 1/21/97
4-10
Registers
PRE.4 for Rev. D
Copyright 1997 by LSI Logic Corporation. All rights reserved.
DES
Destination
15
When this bit is cleared to 0, the destination is the trans-
port buffer. When it is set to 1, the destination is the
DRAM extended channel buffer. Note that the DES set-
tings for PID Index 30 (audio) and PID Index 31 (video)
must be the same.
EI
Enable Interrupt
14
When set to 1, this bit enables an interrupt to be gener-
ated when the PPU nishes processing this PID. The sta-
tus word for this PID is stored in the PID Processor
Status Queue. When reset to 0, this PID does not gener-
ate an interrupt, and no status word is saved in the PID
Status Queue.
ACT
Active
13
When set to 1, the PPU lters the stream for this PID;
otherwise, it does not.
0
Zero
[12:11]
These bits are zero.
1
One
10
This bit must be set to 1.
AF
Post AF
9
When set to 1, this bit indicates that the adaptation eld
in this PID is posted to the MMU. When set to 0, the
adaptation eld is not posted.
AUX
Post to AUX Port
8
When set to 1, the transport packet of this PID is posted
to the AUX port. This is done in parallel to the payload
data and adaptation eld of this packet, which are posted
to the external DRAM or host interface according to the
DES control bit. When set to 0, the transport packet of
this PID is not posted to the AUX port.
RES
Reserved
[7:0]
These bits are reserved.
4.3.3
Audio Splice
PID Value
(ASPV)
The ASPV is a 13-bit read/write register representing the ID of the audio
PID to switch to during a splice operation. The ASPV Register bit eld is
described below.
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