參數(shù)資料
型號: L64007
廠商: LSI CORP
元件分類: 消費家電
英文描述: SPECIALTY CONSUMER CIRCUIT, PQFP160
封裝: PLASTIC, QFP-160
文件頁數(shù): 29/166頁
文件大小: 1015K
代理商: L64007
register
42 Wed May 28 17:37:25 1997
Draft 1/21/97
4-42
Registers
PRE.4 for Rev. D
Copyright 1997 by LSI Logic Corporation. All rights reserved.
AFINT
Adaptation Field MMU Interrupt
15
This bit indicates that the Adaptation Field MMU interrupt
has occurred when set to 1.
RES
Reserved
14
This bit is reserved.
PIDINT
PSI PID Section End Interrupt
[13:0]
Each bit corresponds to the respective PID number. A bit
set to 1 indicates that the corresponding PID has issued
a section end interrupt.
4.8.12
Splice
Countdown
Register (SPR)
This 8-bit register stores the value of the splice counter, which is trans-
mitted with the transport packet that carries the video of the program
being decoded. Whenever the L64007 detects the SPI bit in the transport
adaptation eld, the splice count eld is extracted and stored in the SPR.
EOPSF
End of Packet Splic Flag
15
This ag indicates that the end of packet has occurred
ASF
Audio Splice Flag
14
This bit indicates an audio splice.
VSF
Video Splice Flag
13
This bit indicates a video splice.
RES
Reserved
[12:8]
These bits are reserved.
SPR
Splice Countdown Register
[7:0]
The value of the splice counter is read from the SPI bit
in the transport adaptation eld and stored in this 8-bit
register.
4.8.13
Frequency
Synthesizer Cell
(FSC) Control
Register
This 16-bit write-only register set the control bits for the frequency syn-
thesizer of the audio clock generator (see Section 2.8, Audio Clock Gen-
erator for more details).
15
14
13
12
8
7
0
EOPSF ASF VSF
RES
SPR
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