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| 型號(hào)： | L64007 |
| 廠商： | LSI CORP |
| 元件分類： | 消費(fèi)家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP160 |
| 封裝： | PLASTIC, QFP-160 |
| 文件頁(yè)數(shù)： | 22/166頁(yè) |
| 文件大小： | 1015K |
| 代理商： | L64007 |
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register
36 Wed May 28 17:37:25 1997
Draft 1/21/97
4-36
Registers
PRE.4 for Rev. D
Copyright 1997 by LSI Logic Corporation. All rights reserved.
TR_EN
Transfer Enable
0
When set to 1, this bit enables the transfer operation
between the external DRAM device and the L64007 inter-
nal DMA FIFO. This bit is effective only when the
TR_SEL bit is reset to 0, which means that the transfer
service through the DMA FIFO is devoted completely to
the external DRAM. When the bit is set to 1, the MMU
transfers data blocks in a size specied in the
TR_BLOCK eld. TR_EN enables only the internal trans-
fer between the DMA FIFO and the MMU block; it does
not start the DMA transfer operation. Using only TR_EN,
the user can transfer data using the host processor and
not DMA controller services. This can be done by inter-
rupt or by polling the SSR bits. After reset, the bit is 0.
When set to 0, this bit disables data transfer between the
DRAM and the DMA FIFO.
4.8.7
DMA Pointer
Low Register
(DPLR)
The DPLR is a 16-bit read or write register that species the DRAM start
address location of the transfer operation. The value in this register is the
lower 16-bit value of the 20-bit address register. The 4 MSBs are speci-
ed in the TR_MSB eld of the DTCR. Even if the rst 512 words are
devoted for internal L64007 registers, the start address in the DRAM is
0. After reset, the value is 0.
TR_LSB
Transfer LSB
[15:0]
This 16-bit eld species the start address of the transfer
operation. These 16 bits, together with the 4 bits in
TR_MSB eld, form the 20-bit address register. After
reset, the value is 0.
4.8.8
DRAM
Conguration
Register (DCR)
The DCR determines the operation mode between the L64007 DRAM
interface and the external DRAM device. The user must program the
DCR according to the DRAM device that is attached to the L64007.
15
0
TR_LSB
15
14
12
11
10
9
8
7
4
3
0
RES
CMODE
CYC
PAGE
REFR
RAS_CNT
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