參數(shù)資料
型號: L64007
廠商: LSI CORP
元件分類: 消費家電
英文描述: SPECIALTY CONSUMER CIRCUIT, PQFP160
封裝: PLASTIC, QFP-160
文件頁數(shù): 77/166頁
文件大?。?/td> 1015K
代理商: L64007
Arch
10 Wed May 28 17:36:23 1997
Draft 1/21/97
2-10
Architecture
PRE.4 for Rev. D
Copyright 1997 by LSI Logic Corporation. All rights reserved.
For the common VCxO, 2.5 V in its voltage control input results in an
output clock of 27 MHz. For the Sigma Delta Modulator register (Section
4.7.1, Sigma Delta Modulator (SDM)), the middle range value, 0x9140,
produces a train of pulses with a 50% duty cycle between the LOW and
HIGH times (see Figure 2.8). The error value programmed into the
Sigma Delta Register causes the train of pulses output to change its
LOW to HIGH duty cycle ratio. The RC lter averages the output from
the Sigma Delta Register and passes it to the VCxO; this makes the
master clock frequency go up or down.
Figure 2.8
Effect of Sigma Delta
Modulator on Output
Clock
R = 1 K +-5%
5 V
R = 6 K +-5%
Sigma Delta
Output Pin
VCxO
Input
Voltage
PIN
C = 1
F
C = 0.01
F
Ceramic
Tantalum
Open Drain
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