參數(shù)資料
型號: L64007
廠商: LSI CORP
元件分類: 消費家電
英文描述: SPECIALTY CONSUMER CIRCUIT, PQFP160
封裝: PLASTIC, QFP-160
文件頁數(shù): 28/166頁
文件大小: 1015K
代理商: L64007
register
41 Wed May 28 17:37:25 1997
Draft 1/21/97
L64007 MPEG-2, DVB, JSAT Transport Demultiplexer Technical Manual
4-41
PRE.4 for Rev. D
Copyright 1997 by LSI Logic Corporation. All rights reserved.
The FIFO ags (bits [15:10]) are all “sticky”, meaning that when a condi-
tion is met to set the corresponding ag in the SSR to one, the ag will
remain set after the condition goes away. All ags are reset to zero when
the SSR is read. However, if the condition which caused the ag to be
set is still true after reading the SSR, the corresponding ag will be set
to one 2 cycles following an SSR read.
4.8.10
MMU Status
Register (MSR)
LOW
This register contains the lower 16 bits of status information for the MMU.
It indicates the PSI sections that have been posted to the cyclic buffer
since the last read of this register. A read from this register will result in
it being cleared.
After reset, this register is set to 0.
MSR LOW.
4.8.11 MMU
Status Register
(MSR) HIGH
This register contains the upper16 bits of status information for the MMU.
It indicates the PSI sections that have been posted to the cyclic buffer
since the last read of this register. A read from this register results in it
being cleared.
After reset, this register is set to 0.
PSQ_VAL
PSQ_CNT
Status Words in PSQ
100
1
101
2
110
3
111
4
0XX
0
15
0
PID [15:0] Interrupts
15
14
13
0
AFINT RES
PID [29:16] Interrupts
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