參數(shù)資料
型號: L64007
廠商: LSI CORP
元件分類: 消費(fèi)家電
英文描述: SPECIALTY CONSUMER CIRCUIT, PQFP160
封裝: PLASTIC, QFP-160
文件頁數(shù): 124/166頁
文件大?。?/td> 1015K
代理商: L64007
Arch
52 Wed May 28 17:36:23 1997
Draft 1/21/97
2-52
Architecture
PRE.4 for Rev. D
Copyright 1997 by LSI Logic Corporation. All rights reserved.
Figure 2.46
DRAM Access
Through L64007
Cache
2.5.1
DMA Transfers
The host DMA transfer mode is initiated when the host processor sets
the TR_EN bit (in the DMA Control Register) to HIGH. A DMA transfer
can be done on data coming from the PPU or on data residing in the
external DRAM device. Resource selection is done by a special selection
bit in the DMA Control Register, TR_SEL. The direction of the DMA oper-
ation is determined by the TR_DIR bit in the DMA Control Register. DMA
handshake is done by two lines: DMA request (DREQ) output, and DMA
acknowledge (DACK). All the DMA data transfers are done in bursts
between the host system and the L64007 internal DMA FIFO. The burst
level is programmable; the number of words transferred in a burst can
vary from 1 to 32. Once a DMA transfer is started, it continues as long
as the TR_EN bit is HIGH. The status of the internal DMA FIFO and the
programmed BURST level determines if the DREQ signal is active or not.
The L64007 expects the DACK signal to toggle on every DMA bus cycle.
All other host processor input control signals are disregarded during an
active DMA bus cycle. Even CS is disregarded during a DMA bus cycle.
PID#n
Write Pointer
Cache Pointer
Cache
Buffer
Host Interface
Burst Level
Fast Page Mode
Transfer
Cache
Controller
Address
Data
External
DRAM
Device
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