參數(shù)資料
型號(hào)： ISP1362
廠商： NXP Semiconductors N.V.
英文描述： Single-chip Universal Serial Bus On-The-Go controller
中文描述： 單芯片通用串行總線和On - The - Go控制器
文件頁數(shù)： 97/150頁
文件大?。?/td> 647K
代理商： ISP1362
Philips Semiconductors
ISP1362
Single-chip USB OTG controller
Product data
Rev. 03
—
06 January 2004
97 of 150
9397 750 12337
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
15.4.5
Hc
μ
PInterruptEnable register (R/W: 25H/A5H)
The bits 9:0 in this register are the same as those in the Hc
μ
PInterrupt register. The
bits in this register are used together with bit 0 of the HcHardwareCon
fi
guration
register to enable or disable the bits in the Hc
μ
PInterrupt register.
At power-on, all the bits in this register are masked with logic 0. This means no
interrupt request output on the interrupt pin INT1 can be generated. When a bit is set
to logic 1, the interrupt for that bit is enabled.
The bit allocation of the register is given in
Table 70
.
Code (Hex): 25
—
read
Code (Hex): A5
—
write
2
ISTL_1_
INT
0
—
no event
1
—
The transaction of the last PTD stored on the ISTL1 buffer has
been completed. The microprocessor is required to read data from
the ISTL1 buffer. The HCD must
fi
rst read the HcBufferStatus
register to check the status of the ISTL1 buffer before reading data
to the microprocessor.
0
—
no event
1
ISTL_0_
INT
1
—
The transaction of the last PTD stored on the ISTL0 buffer has
been completed. The microprocessor is required to read data from
the ISTL0 buffer. The HCD must
fi
rst read the HcBufferStatus
register to check the status of the ISTL0 buffer before reading data
to the microprocessor.
0
—
no event
0
SOF_INT
1
—
The HC is in the SOF state and it indicates the start of a new
frame. The HCD must
fi
rst read the HcBufferStatus register to
check the status of the ISTL buffer before reading data to the
microprocessor. For the microprocessor to perform the DMA
transfer of ISO data from or to the ISTL buffer, the HC must
fi
rst
initialize the HcDMACon
fi
guration register.
Table 69:
Bit
Hc
μ
PInterrupt register: bit description
…
continued
Symbol
Description
Table 70:
Bit
Symbol
Hc
μ
PInterruptEnable register: bit allocation
15
14
13
12
11
10
9
8
reserved
OTG_IRQ_
Interrupt
Enable
0
R/W
1
ISTL_0
Interrupt
Enable
0
R/W
ATL_IRQ_
Interrupt
Enable
0
R/W
0
SOF
Interrupt
Enable
0
R/W
Reset
Access
Bit
Symbol
-
-
7
-
-
6
-
-
5
-
-
4
-
-
3
-
-
2
INTL_IRQ_
Interrupt
Enable
0
R/W
ClkReady
HC
Suspended
Enable
0
R/W
OPR
Interrupt
Enable
0
R/W
EOT
Interrupt
Enable
0
R/W
ISTL_1
Interrupt
Enable
0
R/W
Reset
Access
0
R/W
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