參數(shù)資料
型號： ISP1362
廠商： NXP Semiconductors N.V.
英文描述： Single-chip Universal Serial Bus On-The-Go controller
中文描述： 單芯片通用串行總線和On - The - Go控制器
文件頁數(shù)： 95/150頁
文件大小： 647K
代理商： ISP1362
Philips Semiconductors
ISP1362
Single-chip USB OTG controller
Product data
Rev. 03
—
06 January 2004
95 of 150
9397 750 12337
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
15.4.3
HcTransferCounter register (R/W: 22H/A2H)
Regardless of the programmed I/O (PIO) or DMA data transfer modes, this register is
used to initialize the number of bytes to be transferred to or from the ISTL, INTL or
ATL buffer RAM. For the count value loaded in the register to take effect, the HCD is
required to set bit 7 of the HcDMACon
fi
guration register to HIGH. When the count
value has reached, the HC needs to generate an internal EOT signal to set bit 2 of
the Hc
μ
PInterrupt register, AllEOInterrupt, and update the HcBufferStatus register.
The bit allocation of the HcTransferCounter register is given in
Table 67
.
Code (Hex): 22
—
read
Code (Hex): A2
—
write
15.4.4
Hc
μ
PInterrupt register (R/W: 24H/A4H)
All the bits in this register are active at power-on reset. None of the active bits,
however, will cause an interrupt on the interrupt pin (INT1) unless they are set by the
respective bits in the Hc
μ
PInterruptEnable register and bit 0 of the
HcHardwareCon
fi
guration register is also set.
After this register (24H
–
read) is read, the bits that are active will not be reset until
logic 1 is written to the bits in this register (A4H
–
write) to clear it.
The bits in this register are cleared only when you write to this register indicating the
bits to be cleared. To clear all the enabled bits in this register, the HCD must write
FFH to this register.
The bit allocation of the Hc
μ
PInterrupt register is given in
Table 68
.
Code (Hex): 24
—
read
Code (Hex): A4
—
write
Table 67:
Bit
15 to 0
HcTransferCounter register: bit description
Symbol
Access
CounterValue
[15:0]
Value
0000H
Description
Number of data bytes to be read from or
written to the buffer RAM.
R/W
Table 68:
Bit
Symbol
Reset
Access
Bit
Symbol
Hc
μ
PInterrupt register: bit allocation
15
14
13
12
11
10
9
8
reserved
OTG_IRQ
0
R/W
1
ISTL_0_
INT
0
R/W
ATL_IRQ
0
R/W
0
SOF_INT
-
-
7
-
-
6
-
-
5
-
-
4
-
-
3
-
-
2
INTL_IRQ
ClkReady
HC
Suspended
0
R/W
OPR_Reg
AllEOT
Interrupt
0
R/W
ISTL_1_
INT
0
R/W
Reset
Access
0
0
0
0
R/W
R/W
R/W
R/W
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