參數(shù)資料
型號: ISP1362
廠商: NXP Semiconductors N.V.
英文描述: Single-chip Universal Serial Bus On-The-Go controller
中文描述: 單芯片通用串行總線和On - The - Go控制器
文件頁數(shù): 9/150頁
文件大小: 647K
代理商: ISP1362
Philips Semiconductors
ISP1362
Single-chip USB OTG controller
Product data
Rev. 03
06 January 2004
9 of 150
9397 750 12337
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
V
CC
14
J2
-
supply voltage (3.3 V); it is recommended to connect a decoupling
capacitor of 0.01
μ
F
bit 12 of the bidirectional data bus that connects to the internal
registers and buffer memory of the ISP1362; the bus is in the
high-impedance state when it is idle
bidirectional, push-pull input, three-state output
bit 13 of the bidirectional data bus that connects to the internal
registers and buffer memory of the ISP1362; the bus is in the
high-impedance state when it is idle
bidirectional, push-pull input, three-state output
bit 14 of the bidirectional data bus that connects to the internal
registers and buffer memory of the ISP1362; the bus is in the
high-impedance state when it is idle
bidirectional, push-pull input, three-state output
bit 15 of the bidirectional data bus that connects to the internal
registers and buffer memory of the ISP1362; the bus is in the
high-impedance state when it is idle
bidirectional, push-pull input, three-state output
digital ground
read strobe input; when asserted LOW, it indicates that the HC/DC
driver is requesting a read to the buffer memory or the internal
registers of the HC/DC
input with hysteresis
chip select input (active LOW); enables the HC/DC driver to access
the buffer memory and registers of the HC/DC
input
write strobe input; when asserted LOW, it indicates that the HC/DC
driver is requesting a write to the buffer memory or the internal
registers of the HC/DC
input with hysteresis
for test input and output; pulled HIGH by a 100 k
resistor
bidirectional, push-pull input, three-state output
DMA request output; when active, it signals the DMA controller that a
data transfer is requested by the HC; the active level (HIGH or LOW)
of the request is programmed by using the HcHardwareCon
fi
guration
register (20H/A0H)
If the OneDMA bit of the HcHardwareCon
fi
guration register is set to
logic 1, both the HC and DC DMA channel will be routed to DREQ1
and DACK1.
push-pull output
DMA request output; when active, it signals the DMA controller that a
data transfer is requested by the DC; the active level (HIGH or LOW)
of the request is programmed by using the DcHardwareCon
fi
guration
register (BAH/BBH)
push-pull output
D12
15
J1
I/O
D13
16
K1
I/O
D14
17
K2
I/O
D15
18
J3
I/O
DGND
RD
19
20
K3
J4
-
I
CS
21
K4
I
WR
22
J5
I
TEST0
23
K5
I/O
DREQ1
24
J6
O
DREQ2
25
K6
O
Table 2:
Symbol
[1]
Pin description
continued
Pin
LQFP64
Ball
TFBGA64
Type
[2]
Description
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