參數(shù)資料
型號: ISP1362
廠商: NXP Semiconductors N.V.
英文描述: Single-chip Universal Serial Bus On-The-Go controller
中文描述: 單芯片通用串行總線和On - The - Go控制器
文件頁數(shù): 21/150頁
文件大?。?/td> 647K
代理商: ISP1362
Philips Semiconductors
ISP1362
Single-chip USB OTG controller
Product data
Rev. 03
06 January 2004
21 of 150
9397 750 12337
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
9.4 PIO access to internal control registers
Table 5
shows the I/O port addressing in the ISP1362. The complete I/O port address
decoding should combine with the chip select signal (CS) and the address lines (A1
and A0). The direction of access of I/O ports, however, is controlled by the RD and
WR signals
When RD is LOW, the microprocessor reads data from the data port of the ISP1362
(see
Figure 10
). When WR is LOW, the microprocessor writes command to the
command port or writes data to the data port (see
Figure 11
).
The register structure in the ISP1362 is a command-data register pair structure. A
complete register access needs a command phase followed by a data phase. The
command (also named as the index of a register) is used to inform the ISP1362 about
the register that will be accessed at the data phase.
On the 16-bit data bus of a microprocessor, a command occupies the lower byte and
the upper byte is
fi
lled with zeros (see
Figure 12
).
For 32-bit registers, the access cycle is shown in
Figure 13
. It consists of a command
phase followed by two data phases.
Table 5:
CS
L
L
L
L
I/O port addressing
A1
A0
L
L
L
H
H
L
H
H
Access
R/W
W
R/W
W
Data bus width
16 bits
16 bits
16 bits
16 bits
Description
HC data port
HC command port
DC data port
DC command port
When A1 = L, microprocessor accesses the HC.
When A1 = H, microprocessor accesses the DC.
Fig 10. Microprocessor access to the HC or the DC.
004aaa122
μ
P bus interface
Host bus interface
Device bus interface
BUS INTERFACE
A1
0
1
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