參數(shù)資料
型號: ISP1362
廠商: NXP Semiconductors N.V.
英文描述: Single-chip Universal Serial Bus On-The-Go controller
中文描述: 單芯片通用串行總線和On - The - Go控制器
文件頁數(shù): 20/150頁
文件大?。?/td> 647K
代理商: ISP1362
Philips Semiconductors
ISP1362
Single-chip USB OTG controller
Product data
Rev. 03
06 January 2004
20 of 150
9397 750 12337
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
9.3 DMA mode
The ISP1362 also provides the DMA mode for external microprocessors to access
the internal buffer memory of the ISP1362. The DMA operation enables data to be
transferred between the system memory of a microprocessor and the internal buffer
memory of the ISP1362.
Remark:
The DMA operation must be controlled by the DMA controller of the external
microprocessor system (master).
Figure 9
shows the DMA interface between a
microprocessor system and the ISP1362.
The ISP1362 provides two DMA channels. The DMA channel 1 (controlled by the
DREQ1 and DACK1 signals) is for the DMA transfer between the system memory of
a microprocessor and the internal buffer memory of the ISP1362 HC. The DMA
channel 2 (controlled by the DREQ2 and DACK2 signals) is for the DMA transfer
between the system memory of a microprocessor and the internal buffer memory of
the ISP1362 DC. The ISP1362 provides an internal End-Of-Transfer (EOT) signal to
terminate the DMA transfer.
Fig 8.
PIO interface between a microprocessor and the ISP1362.
004aaa042
D[15:0]
RD
WR
CS
A2
IRQ2
MICRO-
PROCESSOR
ISP1362
D[15:0]
μ
P bus interface
RD
WR
CS
A1
A1
IRQ1
A0
INT1
INT2
Fig 9.
DMA interface between a microprocessor and the ISP1362.
004aaa043
D[15:0]
RD
WR
DACK1
DREQ1
MICRO-
PROCESSOR
ISP1362
D[15:0]
μ
P bus interface
RD
WR
DACK1
DREQ1
DACK2
DREQ2
DACK2
DREQ2
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