參數(shù)資料
型號(hào): ISP1362
廠商: NXP Semiconductors N.V.
英文描述: Single-chip Universal Serial Bus On-The-Go controller
中文描述: 單芯片通用串行總線和On - The - Go控制器
文件頁數(shù): 12/150頁
文件大?。?/td> 647K
代理商: ISP1362
Philips Semiconductors
ISP1362
Single-chip USB OTG controller
Product data
Rev. 03
06 January 2004
12 of 150
9397 750 12337
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
[1]
[2]
[3]
Symbol names with an overscore (for example, NAME) represent active LOW signals.
All I/O pads are 5 V tolerant.
In the OTG mode, this pin is pulled down by an internal resistor.
AGND
V
CC
51
52
A8
B7
-
-
analog ground; used for OTG ATX
supply voltage (3.3 V); it is recommended to connect a decoupling
capacitor of 0.01
μ
F
charge pump capacitor pin 1; low ESR; see
Section 11.6
charge pump capacitor pin 2; low ESR; see
Section 11.6
analog input and output
CP_CAP1
CP_CAP2
V
BUS
53
54
55
A7
B6
A6
AI/O
AI/O
I/O
OTG mode
built-in charge pump output or V
BUS
voltage
comparators input; connect to pin V
BUS
of the OTG connector
DC mode
input as V
BUS
sensing; connect to pin V
BUS
of the
upstream connector
HC mode
not used; leave open
supply reference voltage (5 V); to be used together with built-in
overcurrent circuit; when built-in overcurrent circuit is not in use, this
pin can be tied to V
CC
; it is recommended to connect a decoupling
capacitor of 0.01
μ
F
digital ground
supply voltage (3.3 V); it is recommended to connect a decoupling
capacitor of 0.01
μ
F
for test input and output, pulled to GND by a 10 k
resistor
bidirectional, push-pull input, three-state output
for test input and output, pulled to GND by a 10 k
resistor
bidirectional, push-pull input, three-state output
command or data phase
input
LOW
PIO bus of the HC is selected
V
DD_5V
56
B5
I
DGND
V
CC
57
58
A5
B4
-
-
TEST1
59
A4
I/O
TEST2
60
B3
I/O
A0
61
A3
I
A1
62
B2
I
HIGH
PIO bus of the DC is selected
input
bit 0 of the bidirectional data bus that connects to the internal registers
and buffer memory of the ISP1362; the bus is in the high-impedance
state when it is idle
bidirectional, push-pull input, three-state output
bit 1 of the bidirectional data bus that connects to the internal registers
and buffer memory of the ISP1362; the bus is in the high-impedance
state when it is idle
bidirectional, push-pull input, three-state output
D0
63
A2
I/O
D1
64
A1
I/O
Table 2:
Symbol
[1]
Pin description
continued
Pin
LQFP64
Ball
TFBGA64
Type
[2]
Description
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