參數(shù)資料
型號： IBM038329NL6B
廠商： IBM Microeletronics
英文描述： 256K x 32 Synchronous Graphics RAM(256K x 32 高性能8M位CMOS同步動態(tài)RAM（帶內(nèi)置的圖形性能）)
中文描述： 256K × 32同步圖形RAM（256K × 32位高性能800萬的CMOS同步動態(tài)隨機(jī)存儲器（帶內(nèi)置的圖形性能））
文件頁數(shù)： 31/66頁
文件大?。?/td> 952K
代理商： IBM038329NL6B
IBM038329NL6B
IBM038329NP6B
256K x 32 Synchronous Graphics RAM
03K4292.E35604
Revised 3/98
IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 31 of 66
Read Command (RD)
The following pages describe in detail the Read operations with the help of timing diagrams for various
cases.
A Read bursts is initiated with a Read command. The starting column address and the bank address are pro-
vided with the Read command and Auto Precharge is either enabled or disabled for that burst access. Upon
completion of a burst, assuming no other commands have been initiated, the DQs will go to High-Z. A Full
Page Burst will continue until terminated (at the end of the page it will wrap to column 0 and continue).
Various cases of Reads are shown. The user can use latencies of one, two or three depending upon the sys-
tem clock. A fixed-length Read Burst may be followed by or truncated with a Write burst or Block Write com-
mand (provided that Auto Precharge was not activated) and a Full Page Read burst may be truncated by a
Write burst or Block Write command. The Write burst may be initiated on the clock edge immediately follow-
ing the last (or last desired) data element from the Read burst, provided that I/O contention can be avoided.
It
is generally a good design practice that a single cycle delay must occur between the last data read
and the Write command.
The DQM inputs can be used to avoid I/O contention as shown in the figure labeled Read Followed by a Write
with Extra Clock Cycle on page 37. The DQMs must be asserted High at least two clocks (DQM latency is two
clocks for output buffers) prior to the Write command to suppress data-out due to the previous Read com-
mand. Once the Write command is registered, the output buffers will go to High-Z (or remain High-Z) regard-
less of the state of DQM signals. The DQM signals must be de-asserted (DQM latency is zero clocks for input
buffers) on the same cycle as a Write command to ensure that the written data is not masked. The figure
labeled Read Followed by a Write (or Block Write) on page 36 shows the case where the clock frequency
allows for bus contention to be avoided without adding a NOP cycle, and the one labeled Read Followed by a
Write with Extra Clock Cycle on page 37 shows the case where the additional NOP is needed.
Either a fixed-length or a full-page Read burst can be truncated with a Precharge command to the same
bank. Note that the Precharge command should be issued one cycle before the clock edge at which the last
desired data is valid. A subsequent command cannot be issued to the same bank until t
RP
is met. Part of the
row precharge time is hidden during the access of the last data element. An Auto Precharge command can
be used in place of the Precharge command for fixed length bursts. The disadvantage of the Auto Precharge
command is that it does not truncate fixed-length bursts and does not apply to Full Page Bursts.The disad-
vantage of the Precharge command is that it requires the command and address busses to be available at
the appropriate time to issue the command.
Either a fixed-length or a full-page Read burst can be terminated with the Burst Terminate command. The
fixed-length Burst with Auto Precharge cannot be truncated by the Burst Terminate command.
The Burst
Terminate command should be issued one cycle before the positive clock edge at which the last
desired data element is valid.
Logic Table for Read Command
Mnemonic
CKE
CS
RAS
CAS
WE
DSF
DQM
BA (A9)
A8
A7-A0
RD
H
L
H
L
H
L
0/1
BS
L
Column
RDA
H
L
H
L
H
L
0/1
BS
H
Column
相關(guān)PDF資料
PDF描述
IBM038329NP6B 256K x 32 Synchronous Graphics RAM(256K x 32 高性能8M位CMOS同步動態(tài)RAM（帶內(nèi)置的圖形性能）)
IBM041812PQKB 64K X 18 BURST SRAM(64K X 18高性能可猝發(fā)同步CMOS靜態(tài)RAM)
IBM041813PPLB 64K X 18 BURST PIPELINE SRAM(1M (64K X 18)同步可猝發(fā)流水線式線式高性能靜態(tài)RAM)
IBM041813PQKB 64K X 18 Burst Pipeline SRAM(1M（64K X 18）高性能同步可猝發(fā)管線式靜態(tài)RAM)
IBM041814PPLB 64K X 18 BURST SRAM(1M (64K X 18)同步可猝發(fā)高性能靜態(tài)RAM)
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
IBM038329NQ6A-7R5 制造商:IBM 功能描述:
IBM041812PQKB10 制造商:IBM 功能描述:*
IBM041812PQKB11 制造商:IBM 功能描述:*
IBM041813PQKB5 制造商:IBM 功能描述:
IBM0418A4ACLAA-4F 制造商:IBM 功能描述:
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