參數(shù)資料
型號(hào): IBM041813PQKB
廠商: IBM Microeletronics
英文描述: 64K X 18 Burst Pipeline SRAM(1M(64K X 18)高性能同步可猝發(fā)管線式靜態(tài)RAM)
中文描述: 64K的X 18爆裂管道的SRAM(100萬(64K的X 18)高性能同步可猝發(fā)管線式靜態(tài)內(nèi)存)
文件頁數(shù): 1/15頁
文件大?。?/td> 217K
代理商: IBM041813PQKB
50H5206
SA14-4665-02
Revised 9/97
IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 1 of 15
IBM041813PQKB
Preliminary
64K X 18 BURST PIPELINE SRAM
Features
64K x 18 Organization
0.5
μ
CMOS Technology
Synchronous Burst Mode of Operation Compati-
ble with i486
TM
and Pentium
TM
Processors
Supports Pentium
TM
Processor Address
Pipelining
Common I/O and Registered Outputs
Single +3.3V
±
5% Power Supply and Ground
LVTTL I/O Compatible
Fast OE times: 4, 5ns
Registered Addresses, Data Ins, Control sig-
nals, and Outputs
Asynchronous Output Enable
Self-Timed Write Operation and Byte Write
Capability
Low Power Dissipation
- 1.3 W Active at 100MHz
- 90 mW Standby
100 Pin Thin Quad Flat Pack Package
5V Tolerant I/O
Description
IBM Microelectronics 1M SRAM is a Synchronous
Burstable Pipelined, high performance CMOS Static
RAM that is versatile, wide I/O, and achieves 4 nsec
access. A single clock is used to initiate the
read/write operation and all internal operations are
self-timed. At the rising edge of the Clock, all
Addresses, Data Ins and Control Signals are regis-
tered internally. Burst mode operation, compatible
with the i486
TM
and Pentium
TM
Processor’s
sequence, is accomplished by integrating input reg-
isters, internal 2-bit burst counter and high speed
SRAM in a single chip. Burst reads are initiated with
either ADSP or ADSC being LOW with a valid
address during the rising edge of clock. Data from
this address plus the three subsequent addresses
will be output. The chip is operated with a single
+3.3 V power supply and is compatible with LVTTL
I/O interfaces.
IBM043614PQK32K x 36Burst (PowerPC), TQFP package.
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