參數(shù)資料
型號(hào): IBM041813PQKB
廠商: IBM Microeletronics
英文描述: 64K X 18 Burst Pipeline SRAM(1M(64K X 18)高性能同步可猝發(fā)管線式靜態(tài)RAM)
中文描述: 64K的X 18爆裂管道的SRAM(100萬(wàn)(64K的X 18)高性能同步可猝發(fā)管線式靜態(tài)內(nèi)存)
文件頁(yè)數(shù): 8/15頁(yè)
文件大?。?/td> 217K
代理商: IBM041813PQKB
IBM041813PQKB
64K X 18 BURST PIPELINE SRAM
Preliminary
IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 8 of 15
50H5206
SA14-4665-02
Revised 9/97
AC Characteristics
(T
A
=0 to +70
°
C, V
DD
=3.3V
±
5%, Units in nsec)
Parameter
Symbol
-4
-5
Notes
Min.
Max.
Min.
Max.
Cycle Time
t
CYCLE
10.0
10.0
Clock Pulse High
t
CH
3.0
3.0
Clock Pulse Low
t
CL
3.0
3.0
Clock to Output Valid
t
CQ
4.0
5.0
1
Address Status Controller Setup Time
t
ADSCS
2.5
2.5
Address Status Controller Hold Time
t
ADSCH
0.5
0.5
Address Status Processor Setup Time
t
ADSPS
2.5
2.5
Address Status Processor Hold Time
t
ADSPH
0.5
0.5
Advance Setup Time
t
ADVS
2.5
2.5
Advance Hold Time
t
ADVH
0.5
0.5
Address Setup Time
t
AS
2.5
2.5
Address Hold Time
t
AH
0.5
0.5
Chip Selects Setup Time
t
CSS
2.5
2.5
Chip Selects Hold Time
t
CSH
0.5
0.5
Write Enables Setup Time
t
WES
2.5
2.5
Write Enables Hold Time
t
WEH
0.5
0.5
Data In Setup Time
t
DS
2.5
2.5
Data In Hold Time
t
DH
0.5
0.5
Data Out Hold Time
t
CQX
0.75
0.75
1
Clock High to Output High-Z
t
CHZ
5.0
5.5
1, 2, 3
Clock High to Output Active
t
CLZ
0.5
0.5
1, 2, 3
Output Enable to High-Z
t
OHZ
2.0
6.0
2.0
6.5
1, 2
Output Enable to Low-Z
t
OLZ
0.25
0.25
1, 2
Output Enable to Output Valid
t
OQ
4.0
5.0
1
1. See AC Test Loading figure on page 9.
2. T
OHZ
, T
OLZ
, T
CHZ
and T
CLZ
transitions are measured
±
200 mV from steady state voltage. See AC Test Loading figure 2 on page
11.
3. In depth expansion applications where one SRAM is selected and the other is not, bus contention will not occur because T
CLZ
is
measured from the second rising clock edge while T
CHZ
is measured from the first rising clock edge.
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