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參數(shù)資料
| 型號(hào)： | IBM041813PQKB |
| 廠商： | IBM Microeletronics |
| 英文描述： | 64K X 18 Burst Pipeline SRAM(1M（64K X 18）高性能同步可猝發(fā)管線式靜態(tài)RAM) |
| 中文描述： | 64K的X 18爆裂管道的SRAM（100萬(wàn)（64K的X 18）高性能同步可猝發(fā)管線式靜態(tài)內(nèi)存） |
| 文件頁(yè)數(shù)： | 13/15頁(yè) |
| 文件大小： | 217K |
| 代理商： | IBM041813PQKB |
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IBM041813PQKB
Preliminary
64K X 18 BURST PIPELINE SRAM
50H5206
SA14-4665-02
Revised 9/97
IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 13 of 15
The IBM041813PQK has the pins connected in the manner indicated in the Current Connections (x18) and is
also JEDEC complaint. Future Connections refers to the evolution on the JEDEC standard for subsequent
part numbers.
Connect Compatibility for 64K x18 and Future 64K x 16 & 64K x 18
TQFP PIN #
Current Connections (x18)
Future Connections (x16 & x18)
Function
4,27,54,77
NC
V
DDQ
Output Power Supply
5,26,55,76
NC
V
SS
Ground
14
NC
Low or High, NC for most vendors but
Low or High to comply to the JEDEC
standard.
FT, FLow thru or Pipeline function, tie
Low for flow thru, High for Pipeline
24
DQP2
NC or DQ in x18
Parity bit for second byte
31
NC
Low or High
LB Linear Burst Order, This pin must be
tied low for linear(PowerPC), High for
Interleave (Pentium)
64
NC
Low or High. Low allows normal opera-
tion.
ZZ, Asynchronous Sleep Mode, Tie to
ground for normal function, V
DDQ
for
sleep mode (Low power state)
74
DQP1
NC or DQ in x18
Parity bit for first byte
87
NC
Low or BWE, Tie low if function not usedbytes to be written.
88
NC
Low or GW, Tie High if function not usedbytes to occur with single pin.
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| IBM041814PPLB | 64K X 18 BURST SRAM(1M (64K X 18)同步可猝發(fā)高性能靜態(tài)RAM) |
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相關(guān)代理商/技術(shù)參數(shù) |
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| IBM041813PQKB5 | 制造商:IBM 功能描述: |
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