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參數(shù)資料
| 型號(hào)： | IBM041814PQKB |
| 廠商： | IBM Microeletronics |
| 英文描述： | 64K X 18 BURST SRAM(1M（64K X 18）高性能同步可猝發(fā)CMOS靜態(tài)RAM) |
| 中文描述： | 64K的X 18爆的SRAM（100萬（64K的X 18）高性能同步可猝發(fā)的CMOS靜態(tài)RAM）的 |
| 文件頁數(shù)： | 1/14頁 |
| 文件大?。?/td> | 218K |
| 代理商： | IBM041814PQKB |
50H5205
SA14-4664-01
Revised 9/97
IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 1 of 14
IBM041814PQKB
64K X 18 BURST SRAM
Preliminary
Features
64K x 18 Synchronous Burst Mode SRAM
0.5
μ
CMOS Technology
Synchronous Burst Mode of Operation Compati-
ble with PowerPC
TM
Processors
LVTTL I/O Compatible with Common I/O
Single +3.3 V
±
5% Power Supply and Ground
Registered Addresses, Data Ins and Control
Signals
5 V Tolerant I/O
Asynchronous Output Enable
Self-Timed Write Operation and Byte Write
Capability
Low Power Dissipation
- 1.1 W Active at 83MHz
- 90 mW Standby
100 Pin Thin Quad Flat Pack
Description
IBM Microelectronics 1M SRAM is a Synchronous
Burstable, high performance CMOS Static RAM that
is versatile, wide I/O, and achieves 8 nsec access. A
single clock is used to initiate the read/write opera-
tion and all internal operations are self-timed. At the
rising edge of the Clock, all Addresses, Data Ins and
Control Signals are registered internally. Burst mode
operation, compatible with PowerPC
TM
Processor’s
sequence, is accomplished by integrating input reg-
isters, internal 2-bit burst counter and high speed
SRAM in a single chip. Burst reads are initiated with
either ADSP or ADSC being LOW with a valid
address during the rising edge of clock. Data from
this address plus the three subsequent addresses
will be output. The chip is operated with a single
+3.3 V power supply and is compatible with LVTTL
I/O interfaces.
IBM043614PQK32K x 36Burst (PowerPC), TQFP package.
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