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參數(shù)資料
| 型號： | IBM0436A80QLAB |
| 廠商： | IBM Microeletronics |
| 英文描述： | 8Mb( 256K x 36 ) SRAM(8Mb( 256K x 36 )同步CMOS靜態(tài)RAM) |
| 中文描述： | 8MB的（256K × 36）的SRAM（8兆（256K × 36）同步的CMOS靜態(tài)RAM）的 |
| 文件頁數(shù)： | 1/5頁 |
| 文件大?。?/td> | 67K |
| 代理商： | IBM0436A80QLAB |
cfth3316.01
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IBM0418A80QLAB
IBM0418A40QLAB
IBM0436A80QLAB
IBM0436A40QLAB
Preliminary
8Mb (256Kx36 & 512x18) and 4Mb (128Kx36 & 256Kx18) SRAM
Features
256K x 36 or 512K x 18 Organizations
128K x 36 or 256K x 18 Organizations
0.25 Micron CMOS Technology
Synchronous Flow Thru Mode of Operation with
Self-Timed Late Write
Differential HSTL Input Clocks (K, K)
Differential HSTL Output Clocks (C, C)
+3.3V Power Supply, Ground, 1.6V V
DDQ
, and
0.95V V
REF
HSTL Input and Output levels
Registered Addresses, Write Enables, Synchro-
nous Select, and Data Ins.
Common I/O
Asynchronous Output Enable and Power Down
Inputs
Boundary Scan using limited set of JTAG
1149.1 functions
Byte Write Capability & Global Write Enable
7 x 17 Bump Ball Grid Array Package with
SRAM JEDEC Standard Pinout and Boundary
Scan Order
Programmable Impedance Output Drivers
Description
The 4Mb and 8Mb SRAM
S
are Synchronous
Flowthru Mode, high-performance CMOS Static
Random Access Memories that are versatile and
wide I/O, and can achieve 3ns cycle times. Differen-
tial K clocks are used to initiate the read/write opera-
tion and all internal operations are self-timed. At the
rising edge of the K clock, all Addresses, Write-
Enables, Sync Select, and Data Ins are registered
internally. Differential clocks C and C are used to
control the Output Data hold time by allowing output
data to change after the rising edge of the C clock.
An internal Write buffer allows write data to follow
one cycle after addresses and controls. The chip is
operated with a single +3.3V power supply and is
compatible with HSTL I/O interface.
.
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