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參數(shù)資料
| 型號： | IBM0436A81QLAB |
| 廠商： | IBM Microeletronics |
| 英文描述： | 8Mb (256K x 36 ) SRAM(8M位 ( 256Kx 36) 同步流水線式高性能CMOS靜態(tài)RAM) |
| 中文描述： | 8MB的（256K × 36）的SRAM（800萬位（256Kx 36）同步流水線式高性能的CMOS靜態(tài)RAM）的 |
| 文件頁數(shù)： | 1/5頁 |
| 文件大?。?/td> | 78K |
| 代理商： | IBM0436A81QLAB |
trrh3316. 01
11/98
IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 3 of 6
IBM0418A81QLAB
IBM0418A41QLAB
IBM0436A81QLAB
IBM0436A41QLAB
Preliminary
8Mb (256Kx36 & 512x18) and 4Mb (128Kx36 & 256Kx18) SRAM
Features
256K x 36 or 512K x 18 organizations
128K x 36 or 256K x 18 organizations
0.25 Micron CMOS technology
Synchronous Pipeline Mode of Operation with
Self-Timed Late Write
Single Differential Extended HSTL Clock
+3.3V Power Supply, Ground, 1.5V V
DDQ
, and
0.75V V
REF
HSTL Input AND Outputs..
Registered Addresses, Write Enables, Synchro-
nous Select, and Data Ins.
Registered Outputs
Common I/O
Asynchronous Output Enable and Power Down
Inputs
Boundary Scan using limited set of JTAG
1149.1 functions
Byte Write Capability and Global Write Enable
7 x 17 Bump Ball Grid Array Package with
SRAM JEDEC Standard Pinout and Boundary
SCAN Order
Programmable Impedance Output Drivers
Description
The 4Mb and 8Mb SRAMs—IBM0436A41QLAB,
IBM0418A41QLAB, IBM0418A81QLAB, and
IBM0436A81QLAB—are Synchronous Pipeline
Mode, high-performance CMOS Static Random
Access Memories that are versatile, have wide I/O,
and can achieve 3ns cycle times. Differential K
clocks are used to initiate the read/write operation
and all internal operations are self-timed. At the ris-
ing edge of the K clock, all Addresses, Write-
Enables, Sync Select, and Data Ins are registered
internally. Data Outs are updated from output regis-
ters off the next rising edge of the K clock. An inter-
nal Write buffer allows write data to follow one cycle
after addresses and controls. The chip is operated
with a single +3.3V power supply and is compatible
with HSTL I/O interfaces.
.
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