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| 型號(hào)： | IBM041814PQKB |
| 廠商： | IBM Microeletronics |
| 英文描述： | 64K X 18 BURST SRAM(1M（64K X 18）高性能同步可猝發(fā)CMOS靜態(tài)RAM) |
| 中文描述： | 64K的X 18爆的SRAM（100萬(wàn)（64K的X 18）高性能同步可猝發(fā)的CMOS靜態(tài)RAM）的 |
| 文件頁(yè)數(shù)： | 4/14頁(yè) |
| 文件大?。?/td> | 218K |
| 代理商： | IBM041814PQKB |
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IBM041814PQKB
64K X 18 BURST SRAM
Preliminary
IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 4 of 14
50H5205
SA14-4664-01
Revised 9/97
Burst SRAM Clock Truth Table
CLK
L
→
H
L
→
H
L
→
H
L
→
H
CS2
H
CS2
X
CS
L
ADSP
L
ADSC
X
ADV
X
WE
X
OE
X
DQ
Operation
High-Z Deselected Cycle
X
L
L
L
X
X
X
X
High-Z Deselected Cycle
H
X
X
X
L
X
X
X
High-Z Deselected Cycle
X
L
X
X
L
X
X
X
High-Z Deselected Cycle
Read from External
Address, Begin Burst
Read from External
Address, Begin Burst
Read from External
Address, Begin Burst
Write to External
Address, Begin Burst
Read from next Add.,
Continue Burst
Write to next Add.,
Continue Burst
Read from Current
Add., Suspend Burst
Write to Current Add.,
Suspend Burst
High-Z Deselect Cycle
Read from next Add.,
Continue Burst
Write to next Add.,
Continue Burst
Read from current
Add., Suspend Burst
Write to current Add.,
Suspend Burst
L
→
H
L
H
L
L
X
X
X
L
Q
L
→
H
L
H
L
L
X
X
X
H
High-Z
L
→
H
L
H
L
H
L
X
H
L
Q
L
→
H
L
H
L
H
L
X
L
X
D
L
→
H
X
X
X
H
H
L
H
L
Q
L
→
H
X
X
X
H
H
L
L
X
D
L
→
H
X
X
X
H
H
H
H
L
Q
L
→
H
X
X
X
H
H
H
L
X
D
L
→
H
X
X
H
X
L
X
X
X
L
→
H
X
X
H
X
H
L
H
L
Q
L
→
H
X
X
H
X
H
L
L
X
D
L
→
H
X
X
H
X
H
H
H
L
Q
L
→
H
X
X
H
X
H
H
L
X
D
1. For a write operation preceded by a read cycle, OE must be HIGH early enough to allow Input Data Setup, and must be kept HIGH
through Input Data Hold Time.
2. WE refers to WEa, WEb.
3. ADSP is gated by CS, and CS is used to block ADSP when CS = V
IH
, as required in applications using Processor Address Pipelin-
ing.
4. All Addresses, Data In and Control signals are registered on the rising edge of CLK.
Burst Sequence Truth Table
External Address
A15-A2
(A1,A0)
Notes
(0,0)
(0,1)
(1,0)
(1,1)
1st Access
A15-A2
(0,0)
(0,1)
(1,0)
(1,1)
2nd Access
A15-A2
(0,1)
(1,0)
(1,1)
(0,0)
3rd Access
A15-A2
(1,0)
(1,1)
(0,0)
(0,1)
4th Access
A15-A2
(1,1)
(0,0)
(0,1)
(1,0)
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