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參數(shù)資料
| 型號： | IBM041814PQKB |
| 廠商： | IBM Microeletronics |
| 英文描述： | 64K X 18 BURST SRAM(1M（64K X 18）高性能同步可猝發(fā)CMOS靜態(tài)RAM) |
| 中文描述： | 64K的X 18爆的SRAM（100萬（64K的X 18）高性能同步可猝發(fā)的CMOS靜態(tài)RAM）的 |
| 文件頁數(shù)： | 12/14頁 |
| 文件大?。?/td> | 218K |
| 代理商： | IBM041814PQKB |
IBM041814PQKB
64K X 18 BURST SRAM
Preliminary
IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 12 of 14
50H5205
SA14-4664-01
Revised 9/97
The IBM041812PQK has the pins connected in the manner indicated in the Current Connections (x18) and is
also JEDEC complaint. Future Connections refers to the evolution on the JEDEC standard for subsequent
part numbers.
Connect Compatibility for 64K x18 and Future 64K x 16 & 64K x 18
TQFP PIN #
Current Connections (x18)
Future Connections (x16 & x18)
Function
4,27,54,77
NC
V
DDQ
Output Power Supply
5,26,55,76
NC
V
SS
Ground
14
NC
Low or High, NC for most vendors but
Low or High to comply to the JEDEC
standard.
FT , FLow thru or Pipeline function, tie
Low for flow thru, High for Pipeline
24
DQP2
NC or DQ in x18
Parity bit for second byte
31
NC
Low or High
LBO , Linear Burst Order, This pin must
be tied low for linear(PowerPC), High for
Interleave (Pentium)
64
NC
Low or High. Low allows normal opera-
tion.
ZZ , Asynchronous Sleep Mode, Tie to
ground for normal function, V
DDQ
for
sleep mode (Low power state)
74
DQP1
NC or DQ in x18
Parity bit for first byte
87
NC
Low or BWE, Tie low if function not usedbytes to be written.
88
NC
Low or GW, Tie High if function not usedbytes to occur with single pin.
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