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參數(shù)資料
| 型號： | IBM041814PPLB |
| 廠商： | IBM Microeletronics |
| 英文描述： | 64K X 18 BURST SRAM(1M (64K X 18)同步可猝發(fā)高性能靜態(tài)RAM) |
| 中文描述： | 64K的X 18爆的SRAM（100萬（64K的X 18）同步可猝發(fā)高性能靜態(tài)內(nèi)存） |
| 文件頁數(shù)： | 1/12頁 |
| 文件大?。?/td> | 236K |
| 代理商： | IBM041814PPLB |
8190739
SA14-4651-04
Revised 9/97
IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 1 of 12
IBM041814PPLB
64K X 18 BURST SRAM
Features
64K x 18 Synchronous Burst Mode SRAM
0.5
μ
CMOS Technology
Synchronous Burst Mode of Operation Compati-
ble with PowerPC
TM
Processors
Single +3.3V
±
5% Power Supply and Ground
LVTTL I/O Compatible
5V Tolerant I/OCommon I/O
Asynchronous Output Enable
Registered Addresses, Data Ins and Control
Signals
Self-Timed Write Operation and Byte Write
Capability
Low Power Dissipation
- 780mW Active at 66MHz
- 90 mW Standby
52 Pin PLCC Package
Description
IBM Microelectronics 1M SRAM is a Synchronous
Burstable, high performance CMOS Static RAM that
is versatile, wide I/O, and achieves 8.5 nsec access.
A single clock is used to initiate the read/write opera-
tion and all internal operations are self-timed. At the
rising edge of the Clock, all Addresses, Data Ins and
Control Signals are registered internally. Burst mode
operation, compatible with PowerPC
TM
Processor’s
sequence, is accomplished by integrating input reg-
isters, internal 2-bit burst counter and high speed
SRAM in a single chip. Burst reads are initiated with
either ADSP or ADSC being LOW with a valid
address during the rising edge of clock. Data from
this address plus the three subsequent addresses
will be output. The chip is operated with a single
+3.3 V power supply and is compatible with LVTTL
I/O interfaces.
Pin Description
A0-A15
Address input
DQ0-DQ17
Data Input/Output (0-8,9-17)
CLK
Clock
WEa
Write Enable, Byte a (0 to 8)
WEb
Write Enable, Byte b (9 to 17)
OE
Output Enable
ADSP
Address Status Processor
ADSC
Address status controller
ADV
Burst Advance Control
CS
ADSP Gated Chip Select
V
DD
Power Supply (+3.3V)
V
SS
Ground
PLCC Pin Assignments
46
45
44
43
42
41
40
38
37
36
35
34
DQ8
DQ7
DQ6
VDD
VSS
DQ5
DQ4
DQ3
DQ2
VSS
VDD
DQ1
DQ0
39
8
9
10
11
12
13
14
16
17
18
19
20
DQ9
DQ10
VDD
VSS
DQ11
DQ12
DQ13
DQ14
VSS
VDD
DQ15
DQ16
DQ17
15
7
6
5
4
3
2
5
5
4
4
4
A
A
C
W
W
A
C
O
A
A
A
5
1
A
A
2
2
2
2
2
2
2
3
3
3
3
A
A
A
A
A
A
A
A
A
A
A
2
2
V
V
IBM041812PPL64K x 18Burst (Pentium), PLCC package.
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