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參數(shù)資料
| 型號： | IBM041812PQKB |
| 廠商： | IBM Microeletronics |
| 英文描述： | 64K X 18 BURST SRAM(64K X 18高性能可猝發(fā)同步CMOS靜態(tài)RAM) |
| 中文描述： | 64K的X 18爆的SRAM（64K的X 18高性能可猝發(fā)同步的CMOS靜態(tài)RAM）的 |
| 文件頁數(shù)： | 1/14頁 |
| 文件大?。?/td> | 218K |
| 代理商： | IBM041812PQKB |
26H4672
SA14-4663-01
Revised 9/97
IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 1 of 14
IBM041812PQKB
64K X 18 BURST SRAM
Preliminary
Features
64K x 18 Synchronous Burst Mode SRAM
0.5
μ
CMOS Technology
Compatible with Pentium
TM
and i486
TM
proces-
sors
Supports Pentium
TM
Address Pipelining
LVTTL I/O Compatible with common I/O
Single +3.3 V
±
5% Power Supply and Ground
Registered Addresses, Data Ins and Control
Signals
5 V Tolerant I/O
Asynchronous Output Enable
Self-Timed Write Operation and Byte Write
Capability
Low Power Dissipation
- 1.1 W Active at 83MHz
- 90 mW Standby
100 Pin Thin Quad Flat Pack
Description
IBM Microelectronics 1M SRAM is a Synchronous
Burstable, high performance CMOS Static RAM that
is versatile, wide I/O, and achieves 8 nanosecond
access. A single clock is used to initiate the
read/write operation and all internal operations are
self-timed. At the rising edge of the Clock, all
Addresses, Data Ins and Control Signals are regis-
tered internally. Burst mode operation, is accom-
plished by integrating input registers, internal 2-bit
burst counter and high speed SRAM in a single chip.
Burst reads are initiated with either ADSP or ADSC
being LOW with a valid address during the rising
edge of clock. Data from this address plus the three
subsequent addresses will be output. The chip is
operated with a single +3.3 V power supply and is
compatible with LVTTL I/O interfaces.
IBM043614PQK32K x 36Burst (PowerPC), TQFP package.
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| IBM041812PQKB10 | 制造商:IBM 功能描述:* |
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