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參數(shù)資料
| 型號(hào)： | IBM041813PPLB |
| 廠(chǎng)商： | IBM Microeletronics |
| 英文描述： | 64K X 18 BURST PIPELINE SRAM(1M (64K X 18)同步可猝發(fā)流水線(xiàn)式線(xiàn)式高性能靜態(tài)RAM) |
| 中文描述： | 64K的X管道爆18的SRAM（100萬(wàn)（64K的X 18）同步可猝發(fā)流水線(xiàn)式線(xiàn)式高性能靜態(tài)內(nèi)存） |
| 文件頁(yè)數(shù)： | 1/12頁(yè) |
| 文件大小： | 219K |
| 代理商： | IBM041813PPLB |
8190738
SA14-4655-04
Revised 9/97
IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 1 of 12
IBM041813PPLB
64K X 18 BURST PIPELINE SRAM
Features
64K x 18 Organization
0.5
μ
CMOS Technology
Synchronous Burst Mode of Operation Compati-
ble with i486
TM
and Pentium
TM
Processors
Supports Pentium
TM
Processor Address
Pipelining
Common I/O and Registered Outputs
Single +3.3V
±
5% Power Supply and Ground
LVTTL I/O Compatible
Fast OE time: 5ns
Registered Addresses, Data Ins, Control sig-
nals, and Outputs
Asynchronous Output Enable
Self-Timed Write Operation and Byte Write
Capability
Low Power Dissipation
- 1.1 W Active at 83 MHz
- 90 mW Standby
52 Lead PLCC Package
5V Tolerant I/O
Description
IBM Microelectronics 1M SRAM is a Synchronous
Burstable Pipelined, high performance CMOS Static
RAM that is versatile, wide I/O, and achieves 5 nsec
access and 12nsec cycle time. A single clock is
used to initiate the read/write operation and all inter-
nal operations are self-timed. At the rising edge of
the Clock, all Addresses, Data Ins and Control Sig-
nals are registered internally. Burst mode operation,
compatible with the i486
TM
and Pentium
TM
Proces-
sor’s sequence, is accomplished by integrating input
registers, internal 2-bit burst counter and high speed
SRAM in a single chip. Burst reads are initiated with
either ADSP or ADSC being LOW with a valid
address during the rising edge of clock. Data from
this address plus the three subsequent addresses
will be output. The chip is operated with a single
+3.3 V power supply and is compatible with LVTTL
I/O interfaces.
Pin Description
A0-A15
Address input
DQ0-DQ17
Data Input/Output (0-8,9-17)
CLK
Clock
WEa
Write Enable, Byte a (0 to 8)
WEb
Write Enable, Byte b (9 to 17)
OE
Output Enable
ADSP
Address Status Processor
ADSC
Address status controller
ADV
Burst Advance Control
CS
ADSP Gated Chip Select
V
DD
Power Supply (+3.3V)
V
SS
Ground
X18 PLCC Pin Array Layout
46
45
44
43
42
41
40
38
37
36
35
34
DQ8
DQ7
DQ6
VDD
VSS
DQ5
DQ4
DQ3
DQ2
VSS
VDD
DQ1
DQ0
39
8
9
10
11
12
13
14
16
17
18
19
20
DQ9
DQ10
VDD
VSS
DQ11
DQ12
DQ13
DQ14
VSS
VDD
DQ15
DQ16
DQ17
15
7
6
5
4
3
2
5
5
4
4
4
A
A
C
W
W
A
C
O
A
A
A
5
1
A
A
2
2
2
2
2
2
2
3
3
3
3
A
A
A
A
A
A
A
A
A
A
A
2
2
V
V
IBM041813PPL64K x 18Burst Pipeline (Pentium), PLCC package.
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