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參數(shù)資料
| 型號： | IBM041813PPLB |
| 廠商： | IBM Microeletronics |
| 英文描述： | 64K X 18 BURST PIPELINE SRAM(1M (64K X 18)同步可猝發(fā)流水線式線式高性能靜態(tài)RAM) |
| 中文描述： | 64K的X管道爆18的SRAM（100萬（64K的X 18）同步可猝發(fā)流水線式線式高性能靜態(tài)內存） |
| 文件頁數(shù)： | 3/12頁 |
| 文件大小： | 219K |
| 代理商： | IBM041813PPLB |
IBM041813PPLB
64K X 18 BURST PIPELINE SRAM
8190738
SA14-4655-04
Revised 9/97
IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 3 of 12
Burst SRAM Clock Truth Table
CLK
CS
ADSP
ADSC
ADV
WE
OE
DQ
Operation
L
→
H
H
X
L
X
X
X
High-Z
Deselected Cycle
L
→
H
L
L
X
X
X
L
Q
Read from External Address, Begin
Burst
L
→
H
L
L
X
X
X
H
High-Z
Read from External Address, Begin
Burst
L
→
H
L
H
L
X
H
L
Q
Read from External Address, Begin
Burst
L
→
H
L
H
L
X
L
X
D
Write to External Address, Begin Burst
L
→
H
X
H
H
L
H
L
Q
Read from next Add., Continue Burst
L
→
H
X
H
H
L
L
X
D
Write to next Add., Continue Burst
L
→
H
X
H
H
H
H
L
Q
Read from Current Add., Suspend
Burst
L
→
H
X
H
H
H
L
X
D
Write to Current Add., Suspend Burst
L
→
H
H
X
H
L
H
L
Q
Read from next Add., Continue Burst
L
→
H
H
X
H
L
L
X
D
Write to next Add., Continue Burst
L
→
H
H
X
H
H
H
L
Q
Read from current Add., Suspend
Burst
1. For a write operation preceded by a read cycle, OE must be HIGH early enough to allow Input Data Setup, and must be kept HIGH
through Input Data Hold Time.
2. WE refers to WEa, WEb.
3. ADSP is gated by CS, and CS is used to block ADSP when CS = V
IH
, as required in applications using Processor Address Pipelin-
ing.
4. All Addresses, Data In and Control signals are registered on the rising edge of CLK.
5. Write cycles will put the bus into High-Z on the first rising clock edge according to the T
CHZ
timing. Deselect cycles will put the bus
into High-Z on the second rising edge of clock according to the T
CHZ
timing. If a deselect cycle occurs and WE is enabled within
the same cycle, the part behaves as though it was in a deselect cycle.
Burst Sequence Truth Table
External Address
A15-A2
(A1,A0)
Notes
(0,0)
(0,1)
(1,0)
(1,1)
1st Access
A15-A2
(0,0)
(0,1)
(1,0)
(1,1)
2nd Access
A15-A2
(0,1)
(0,0)
(1,1)
(1,0)
3rd Access
A15-A2
(1,0)
(1,1)
(0,0)
(0,1)
4th Access
A15-A2
(1,1)
(1,0)
(0,1)
(0,0)
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