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參數(shù)資料
| 型號： | IBM041812PQKB |
| 廠商： | IBM Microeletronics |
| 英文描述： | 64K X 18 BURST SRAM(64K X 18高性能可猝發(fā)同步CMOS靜態(tài)RAM) |
| 中文描述： | 64K的X 18爆的SRAM（64K的X 18高性能可猝發(fā)同步的CMOS靜態(tài)RAM）的 |
| 文件頁數(shù)： | 10/14頁 |
| 文件大?。?/td> | 218K |
| 代理商： | IBM041812PQKB |
IBM041812PQKB
64K X 18 BURST SRAM
Preliminary
IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 10 of 14
26H4672
SA14-4663-01
Revised 9/97
Timing Diagram (Burst Write)
CLK
OE
A2
ADDR
ADV
ADSC
ADSP
CS2
DQ
t
cycle
t
CH
t
CL
A1
D1(A)
D2(A)
D2(B)
D2(B)
t
ADSPS
t
ADSPH
t
ADSCH
t
ADSCS
t
ADVH
t
ADVS
t
ADVH
t
ADVS
t
AH
t
AS
t
AS
t
AH
t
WEH
t
WES
t
CSS
t
CSH
t
OHZ
t
DH
t
DS
t
CHZ
t
DS
t
DH
t
DS
t
DS
t
DH
t
DH
t
CSS
t
CSH
CS2
CS
Notes:
1. D1(A) and D2(A) refer to data written to address A1 and A2.
2. D2(B) refers to data written to a subsequent internal burst counter address.
3. WEa, WEb are don’t cares when ADSP is sampled LOW.
t
CLZ
WEa, WEb
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