參數(shù)資料
型號(hào)： IBM038329NL6B
廠商： IBM Microeletronics
英文描述： 256K x 32 Synchronous Graphics RAM(256K x 32 高性能8M位CMOS同步動(dòng)態(tài)RAM（帶內(nèi)置的圖形性能）)
中文描述： 256K × 32同步圖形RAM（256K × 32位高性能800萬(wàn)的CMOS同步動(dòng)態(tài)隨機(jī)存儲(chǔ)器（帶內(nèi)置的圖形性能））
文件頁(yè)數(shù)： 13/66頁(yè)
文件大?。?/td> 952K
代理商： IBM038329NL6B
IBM038329NL6B
IBM038329NP6B
256K x 32 Synchronous Graphics RAM
03K4292.E35604
Revised 3/98
IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 13 of 66
Functional Description
IBM's 8Mb SGRAM is a dual bank 128K x 32 SDRAM with built-in graphics features including Block Write and
Masked Write. It consists of two banks; eachorganized as 512 rows x 256 columns x 32 bits.
Read and Write accesses are burst oriented. Accesses begin with the registration of an Active command
which is then followed by a Read or Write command. The address bits registered coincident with the Active
command are used to select the bank and the row to be accessed. Address bit BA (A
9
) selects the bank and
address bits A
8
-A
0
select the row. Address bits A
7
-A
0
registered coincident with the Read and Write com-
mand are used to select the starting column location for the burst access.
Block Writes are not burst oriented and always apply to eight column locations selected by A
7
-A
3
. DQs regis-
tered at a Write command are used to mask the selected columns. DQs registered coincident with the Active
command are used as Write-per-Bit mask. DQs registered coincident with the Load Special Mode Register
command are used as Color data (LC bit =1) or Persistent Mask (LM = 1). If LC and LM are both 1 in the
same Load Special Mode Register command cycle, the data of the Mask and the Color Register will be
unknown.
Initialization
SGRAMs must be initialized in a predefined manner to prevent undefined operation. Once power is applied,
the SGRAM requires a 100
μ
s delay prior to activating CKE. All inputs should be held high during this phase
of power up. After a delay of 100
μ
s or more, the CKE pin must be driven high before a positive clock (CLK)
edge. The first command will be registered on the clock edge following t
CKS
.
Both banks must then be precharged by issuing the PREAL command, thereby placing the device in the “all
banks idle” state. Once in the idle state, at least two Auto Refresh cycles must be performed. When the Auto
Refresh cycles are complete, the SGRAM is ready for Mode Register programming. Because the Mode Reg-
ister will power up in an unknown state, it should be programmed prior to performing any operational com-
mand.
相關(guān)PDF資料
PDF描述
IBM038329NP6B 256K x 32 Synchronous Graphics RAM(256K x 32 高性能8M位CMOS同步動(dòng)態(tài)RAM（帶內(nèi)置的圖形性能）)
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
IBM038329NQ6A-7R5 制造商:IBM 功能描述:
IBM041812PQKB10 制造商:IBM 功能描述:*
IBM041812PQKB11 制造商:IBM 功能描述:*
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IBM0418A4ACLAA-4F 制造商:IBM 功能描述:
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