參數(shù)資料
型號： IBM038329NL6B
廠商： IBM Microeletronics
英文描述： 256K x 32 Synchronous Graphics RAM(256K x 32 高性能8M位CMOS同步動態(tài)RAM（帶內(nèi)置的圖形性能）)
中文描述： 256K × 32同步圖形RAM（256K × 32位高性能800萬的CMOS同步動態(tài)隨機(jī)存儲器（帶內(nèi)置的圖形性能））
文件頁數(shù)： 1/66頁
文件大?。?/td> 952K
代理商： IBM038329NL6B
IBM038329NL6B
IBM038329NP6B
256K x 32 Synchronous Graphics RAM
03K4292.E35604
Revised 3/98
IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 1 of 66
Features
Fully synchronous; all signals registered on
positive edge of system clock.
Internal pipelined operation; column address
can be changed every clock cycle.
Dual internal banks for hiding row precharge;
Each bank is 128K x 32.
Programmable burst lengths: 1, 2, 4, 8 or full
page
Burst Read with Single Write
Programmable CAS Latency: 1, 2, 3
8 column Block Write and Write-per-Bit modes
Single Cycle Block Write operation
Two Color Registers
Independent byte operation via DQM0-3
Auto Precharge and Auto Refresh modes
1K Refresh cycles/16ms (Auto or Self Refresh)
LVTTL-compatible inputs and outputs
Single 3.3V
±
0.3V Power Supply
100-pin LQFP and PQFP
Description
The IBM 256K x 32 SGRAM is a high speed 8Mb
CMOS Synchronous DRAM with built-in graphics
features. It is internally configured as a dual bank
128K x 32 DRAM with a synchronous interface (all
signals are registered on the positive edge of the
clock signal CLK). Each bank is organized as 512
rows x 256 columns x 32 bits.
Read and Write operations are burst oriented;
accesses start at a selected location and continue
for a programmed number of locations. By having a
Programmable Mode Register and a Load Special
Mode Register command, the system can choose
Read or Write burst lengths of 1, 2, 4, or 8 locations
or the Full Page with Burst Termination option.
An Auto Precharge function may be enabled to pro-
vide a self-timed precharge that is initiated at the
end of the burst sequence.
The SGRAM uses an internal pipelined architecture
to achieve high speed operation, which also allows
the column address to be changed on every clock
cycle to achieve a high-speed, fully random access.
Precharging one bank while accessing the alternate
bank will hide the precharge cycles, and provide
seamless high speed random operation.
The SGRAM differs from the Synchronous DRAM
(SDRAM) by providing an 8 column Block Write
function and a Write-per-Bit (WPB) function. The
Block Write and WPB functions may be combined
with individual byte enables DQM
0
-DQM
3
.
The part is designed to operate at 3.3V only. An
Auto Refresh mode is provided along with a power
saving Power Down mode. All inputs and outputs
are LVTTL compatible.
Options
Marking
Timing
6R7ns Access (
≤
150 Mhz clock rate)
7R5ns Access (
≤
133 Mhz clock rate)
10ns Access (
≤
100 Mhz clock rate)
-6R7
-7R5
-10
Plastic Package
100-pin LQFP (1.4mm body height)
100-pin PQFP (2.7mm body height)
Key Timing Parameters
Speed
Grade
Clock Frequency
(MHz)
Access
Time (ns)
Setup
Time (ns)
Hold
Time (ns)
-6R7
150
6.5
2.0
1.5
-7R5
133
7
2.5
1.5
-10
100
9
2.5
1.5
IBM038329PQ6256 x 16FP, 2WE. IBM038329NQ6256 x 16EDO, 2WE.
相關(guān)PDF資料
PDF描述
IBM038329NP6B 256K x 32 Synchronous Graphics RAM(256K x 32 高性能8M位CMOS同步動態(tài)RAM（帶內(nèi)置的圖形性能）)
IBM041812PQKB 64K X 18 BURST SRAM(64K X 18高性能可猝發(fā)同步CMOS靜態(tài)RAM)
IBM041813PPLB 64K X 18 BURST PIPELINE SRAM(1M (64K X 18)同步可猝發(fā)流水線式線式高性能靜態(tài)RAM)
IBM041813PQKB 64K X 18 Burst Pipeline SRAM(1M（64K X 18）高性能同步可猝發(fā)管線式靜態(tài)RAM)
IBM041814PPLB 64K X 18 BURST SRAM(1M (64K X 18)同步可猝發(fā)高性能靜態(tài)RAM)
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
IBM038329NQ6A-7R5 制造商:IBM 功能描述:
IBM041812PQKB10 制造商:IBM 功能描述:*
IBM041812PQKB11 制造商:IBM 功能描述:*
IBM041813PQKB5 制造商:IBM 功能描述:
IBM0418A4ACLAA-4F 制造商:IBM 功能描述:
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