參數(shù)資料
型號(hào)： EP7209
廠商： Cirrus Logic, Inc.
英文描述： Ultra-Low-Power Audio Decoder System-on-Chip
中文描述： 超低功耗音頻解碼器系統(tǒng)級(jí)芯片
文件頁數(shù)： 64/128頁
文件大?。?/td> 1382K
代理商： EP7209
EP7209
64
DS453PP2
5.2.5
SYSFLG2 System Status Register 2
ADDRESS: 0x8000.1140
This register is an extension of SYSFLG1, containing status bits for backward compatibility with CL-
PS7111. The bits of the second system status register are defined in
Table 31
.
23
22
21:12
Reserved
3
SS2RXFE
11
10:7
6
UTXFF2
5
SS2TXUF
URXFE2
4
SS2TXFF
UBUSY2
2
RESFRM
Reserved
1
RESVAL
CKMODE
0
SS2RXOF
Bit
Description
0
SS2RXOF
: Master/slave SSI2 RX FIFO overflow. This bit is set when a write is attempted to a full
RX FIFO (i.e., when RX is still receiving data and the FIFO is full). This can be cleared in one of
two ways:
1. Empty the FIFO (remove data from FIFO) and then write to SRXEOF location.
2. Disable the RX (affects of disabling the RX will not take place until a full SSI2 clock
cycle after it is disabled)
RESVAL
: Master/slave SSI2 RX FIFO residual byte present, cleared by popping the residual
byte into the SSI2 RX FIFO or by a new RX frame sync pulse.
RESFRM
: Master/slave SSI2 RX FIFO residual byte present, cleared only by a new RX frame
sync pulse.
SS2RXFE
: Master/slave SSI2 RX FIFO empty bit. This will be set if the 16 x 16 RX FIFO is
empty.
SS2TXFF
: Master/slave SSI2 TX FIFO full bit. This will be set if the 16 x 16 TX FIFO is full. This
will get cleared when data is removed from the FIFO or the EP7209 is reset.
SS2TXUF
: Master/slave SSI2 TX FIFO Underflow bit. This will be set if there is attempt to trans-
mit when TX FIFO is empty. This will be cleared when FIFO gets loaded with data.
CKMODE
: This bit reflects the status of the CLKSEL (PE[2]) input, latched during nPOR. When
low, the PLL is running and the chip is operating in 18.432
–
73.728 MHz mode. When high the
chip is operating from an external 13 MHz clock.
UBUSY2
: UART2 transmitter busy. This bit is set while UART2 is busy transmitting data; it is
guaranteed to remain set until the complete byte has been sent, including all stop bits.
URXFE2
: UART2 receiver FIFO empty. The meaning of this bit depends on the state of the UFI-
FOEN bit in the UART2 bit rate and line control register. If the FIFO is disabled, this bit will be set
when the RX holding register contains is empty. If the FIFO is enabled the URXFE bit will be set
when the RX FIFO is empty.
UTXFF2
: UART2 transmit FIFO full. The meaning of this bit depends on the state of the UFI-
FOEN bit in the UART2 bit rate and line control register. If the FIFO is disabled, this bit will be set
when the TX holding register is full. If the FIFO is enabled the UTXFF bit will be set when the TX
FIFO is full.
1
2
3
4
5
6
11
22
23
Table 31. SYSFLG2
相關(guān)PDF資料
PDF描述
EP7211 HIGH-PERFORMANCE ULTRA-LOW-POWER SYSTEM-ON-CHIP WITH LCD CONTROLLER
EP7211-CP-A HIGH-PERFORMANCE ULTRA-LOW-POWER SYSTEM-ON-CHIP WITH LCD CONTROLLER
EP7211-CV-A HIGH-PERFORMANCE ULTRA-LOW-POWER SYSTEM-ON-CHIP WITH LCD CONTROLLER
EP7212 HIGH-PERFORMANCE, LOW-POWER SYSTEM-ON-CHIP WITH LCD CONTROLLER AND DIGITAL AUDIO INTERFACE(DAI)
EP7212-CB-A HIGH-PERFORMANCE, LOW-POWER SYSTEM-ON-CHIP WITH LCD CONTROLLER AND DIGITAL AUDIO INTERFACE(DAI)
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EP7211 制造商:CIRRUS 制造商全稱:Cirrus Logic 功能描述:HIGH-PERFORMANCE ULTRA-LOW-POWER SYSTEM-ON-CHIP WITH LCD CONTROLLER
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