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| 型號： | EP7209 |
| 廠商： | Cirrus Logic, Inc. |
| 英文描述： | Ultra-Low-Power Audio Decoder System-on-Chip |
| 中文描述： | 超低功耗音頻解碼器系統(tǒng)級芯片 |
| 文件頁數(shù)： | 106/128頁 |
| 文件大小： | 1382K |
| 代理商： | EP7209 |
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EP7209
106
DS453PP2
7. TEST MODES
The EP7209 supports a number of hardware acti-
vated test modes, these are activated by the pin
combinations shown in
Table 59
. All latched sig-
nals will only alter test modes while NPOR is low,
their state is latched on the rising edge of NPOR.
This allows these signals to be used normally dur-
ing various test modes.
Within each test mode, a selection of pins is used as
multiplexed outputs or inputs to provide/monitor
the test signals unique to that mode.
7.1
This mode is selected by nTEST[0] = 1,
nTEST[1] = 0.
Oscillator and PLL Bypass Mode
In this mode all the internal oscillators and PLL are
disabled and the appropriate crystal oscillator pins
become the direct external oscillator inputs bypass-
ing the oscillator and PLL. MOSCIN must be driv-
en by a 36.864 MHz clock source and RTCIN by a
32.768 kHz source.
7.2
This mode is selected by nTEST[0] = 0,
nTEST[1] = 1, Latched nURESET = 0
Oscillator and PLL Test Mode
This test mode will enable the main oscillator and
it will output various buffered clock and test signals
derived from the main oscillator, PLL, and 32-kHz
oscillator. All internal logic in the EP7209 will be
static and isolated from the oscillators, with the ex-
ception of the 6-bit ripple counter used to generate
576 kHz and the Real Time Clock divide chain.
Port A is used to drive the inputs of the PLL direct-
ly, and the various clock and PLL outputs are mon-
itored on the COL pins.
Table 60
defines the
EP7209 signal pins used in this test mode. This
mode is only intended to allow test of the oscilla-
tors and PLL
.
Note that these inputs are inverted
before being passed to the PLL to ensure that the
default state of the port (all zero) maps onto the cor-
rect default state of the PLL (TSEL = 1, XTALON
= 1, PLLON = 1, D0 = 0, D1 = 1, PLLBP = 0). This
state will produce the correct frequencies as shown
in
Table 60
. Any other combinations are for testing
the oscillator and PLL and should not be used in-
circuit.
Test Mode
Latched
nMEDCHG
Latched
PE[0]
Latched
PE[1]
Latched
nURESET
nTEST[0]
nTEST[1]
Normal operation
(32-bit boot)
Normal operation
(8-bit boot)
Normal operation
(16-bit boot)
Alternative test ROM
boot
Oscillator / PLL bypass
Oscillator / PLL test
mode
ICE Mode
System test (all HiZ)
1
0
0
X
1
1
1
1
0
X
1
1
1
0
1
X
1
1
0
X
X
X
1
1
X
X
X
X
1
0
X
X
X
0
0
1
X
X
X
1
0
0
X
X
X
0
0
0
Table 59. EP7209 Hardware Test Modes
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