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參數(shù)資料
| 型號： | EP7209 |
| 廠商： | Cirrus Logic, Inc. |
| 英文描述： | Ultra-Low-Power Audio Decoder System-on-Chip |
| 中文描述： | 超低功耗音頻解碼器系統(tǒng)級芯片 |
| 文件頁數(shù)： | 26/128頁 |
| 文件大?。?/td> | 1382K |
| 代理商： | EP7209 |
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EP7209
26
DS453PP2
3.4.3 Dynamic Clock Switching When in the
PLL Clocking Mode
The clock frequency used for the CPU and the bus-
es is controlled by programming the CLKCTL[1:0]
bits in the SYSCON3 register. When this occurs,
the state controller switches from the current to the
new clock frequency as soon as possible without
causing a glitch on the clock signals. The glitch-
free clock switching logic waits until the clock that
is currently in use and the newly programmed clock
source are both low, and then switches from the
previous clock to the new clock without a glitch on
the clocks.
3.5
When unexpected events arise during the execution
of a program (i.e., interrupt or memory fault) an ex-
ception is usually generated. When these excep-
tions occur at the same time, a fixed priority system
determines the order in which they are handled.
Table 8
shows the priority order of all the excep-
tions.
Interrupt Controller
The EP7209 interrupt controller has two interrupt
types: interrupt request (IRQ) and fast interrupt re-
quest (FIQ). The interrupt controller has the ability
to control interrupts from 22 different FIQ and IRQ
sources. Of these, seventeen are mapped to the IRQ
input and five sources are mapped to the FIQ input.
FIQs have a higher priority than IRQs. If two inter-
rupts are received from within the same group (IRQ
or FIQ), the order in which they are serviced must
be resolved in software. The priorities are listed in
Table 9
. All interrupts are level sensitive; that is,
they must conform to the following sequence.
1) The interrupting device (either external or in-
ternal) asserts the appropriate interrupt.
2) If the appropriate bit is set in the interrupt mask
register, then either a FIQ or an IRQ will be as-
serted by the interrupt controller. (A descrip-
tion for each bit in this register can be found in
INTSR1 Interrupt Status Register 1
).
3) If interrupts are enabled the processor will
jump to the appropriate address.
4) Interrupt dispatch software reads the interrupt
status register to establish the source(s) of the
interrupt and calls the appropriate interrupt ser-
vice routine(s).
5) Software in the interrupt service routine will
clear the interrupt source by some action spe-
cific to the device requesting the interrupt (i.e.,
reading the UART RX register).
The interrupt service routine may then re-enable in-
terrupts, and any other pending interrupts will be
serviced in a similar way. Alternately, it may return
to the interrupt dispatch code, which can check for
any more pending interrupts and dispatch them ac-
cordingly. The
“
End of Interrupt
”
type interrupts
are latched. All other interrupt sources (i.e., exter-
nal interrupt source) must be held active until its re-
spective service routine starts executing. See
‘End
of Interrupt’ Locations
for more details.
Table 9
,
Table 10
and
Table 11
show the names
and allocation of interrupts in the EP7209.
Priority
Highest
.
.
.
.
Exception
Reset
Data Abort
FIQ
IRQ
Prefetch Abort
Undefined Instruction,
Software Interrupt
Lowest
Table 8. Exception Priority Handling
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