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參數(shù)資料
| 型號(hào)： | EP7209 |
| 廠商： | Cirrus Logic, Inc. |
| 英文描述： | Ultra-Low-Power Audio Decoder System-on-Chip |
| 中文描述： | 超低功耗音頻解碼器系統(tǒng)級(jí)芯片 |
| 文件頁數(shù)： | 107/128頁 |
| 文件大?。?/td> | 1382K |
| 代理商： | EP7209 |
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EP7209
DS453PP2
107
7.3
This mode is selected by nTEST0 = 0, nTEST1 =
0, Latched nURESET = 1.
Debug/ICE Test Mode
Selection of this mode enables the debug mode of
the ARM720T. By default, this is disabled which
saves approximately 3% on power.
7.4
This mode selected by nTEST0 = 0, nTEST1 = 0,
Latched nURESET = 0.
Hi-Z (System) Test Mode
This test mode asynchronously disables all output
buffers on the EP7209. This has the effect of re-
moving the EP7209 from the PCB so that other de-
vices on the PCB can be in-circuit tested. The
internal state of the EP7209 is not altered directly
by this test mode.
7.5
Software Selectable Test
Functionality
When bit 11 of the SYSCON register is set high, in-
ternal peripheral bus register accesses are output on
the main address and data buses as though they
were external accesses to the address space ad-
dressed by nCS[5]. Hence, nCS[5] takes on a dual
role, it will be active as the strobe for internal ac-
cesses and for any accesses to the standard address
range for nCS[5]. Additionally, in this mode, the
internal signals shown in
Table 61
are multiplexed
out of the device on port pins.
This test is not intended to be used when LCD
DMA accesses are enabled. This is due to the fact
that it is possible to have internal peripheral bus ac-
tivity simultaneously with a DMA transfer. This
would cause bus contention to occur on the external
bus.
The
‘
Waited clock to CPU
’
is an internally ANDed
source that generates the actual CPU clock. Thus, it
is possible to know exactly when the CPU is being
clocked by viewing this pin. The signals nFIQ and
nIRQ are the two output signals from the internal
interrupt controller. They are input directly into the
ARM720T processor.
Signal
I/O
Pin
Function
TSEL *
I
PA5
PLL test mode
Enable to oscillator circuit
Enable to PLL circuit
Bypasses PLL
Output of RTC oscillator
1 Hz clock from RTC divider chain
36 MHz divided PLL main clock
576 KHz divided from above
Test clock output for PLL
XTLON *
I
PA4
PLLON *
I
PA3
PLLBP
I
PA0
RTCCLK
O
COL0
CLK1
O
COL1
OSC36
O
COL2
CLK576K
O
COL4
VREF
O
COL6
Table 60. Oscillator and PLL Test Mode Signals
Signal
I/O
Pin
Function
CLK
O
PE0
Waited clock to CPU
nFIQ interrupt to CPU
nIRQ interrupt to CPU
nFIQ
O
PE1
nIRQ
O
PE2
Table 61. Software Selectable Test Functionality
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PDF描述 |
|---|---|
| EP7211 | HIGH-PERFORMANCE ULTRA-LOW-POWER SYSTEM-ON-CHIP WITH LCD CONTROLLER |
| EP7211-CP-A | HIGH-PERFORMANCE ULTRA-LOW-POWER SYSTEM-ON-CHIP WITH LCD CONTROLLER |
| EP7211-CV-A | HIGH-PERFORMANCE ULTRA-LOW-POWER SYSTEM-ON-CHIP WITH LCD CONTROLLER |
| EP7212 | HIGH-PERFORMANCE, LOW-POWER SYSTEM-ON-CHIP WITH LCD CONTROLLER AND DIGITAL AUDIO INTERFACE(DAI) |
| EP7212-CB-A | HIGH-PERFORMANCE, LOW-POWER SYSTEM-ON-CHIP WITH LCD CONTROLLER AND DIGITAL AUDIO INTERFACE(DAI) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| EP7209-CB-D | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| EP7209-CV-D | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| EP7211 | 制造商:CIRRUS 制造商全稱:Cirrus Logic 功能描述:HIGH-PERFORMANCE ULTRA-LOW-POWER SYSTEM-ON-CHIP WITH LCD CONTROLLER |
| EP7211(208LQFP) | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Logic IC |
| EP7211(256PBGA) | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Logic IC |
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