參數(shù)資料
型號: EP7209
廠商: Cirrus Logic, Inc.
英文描述: Ultra-Low-Power Audio Decoder System-on-Chip
中文描述: 超低功耗音頻解碼器系統(tǒng)級芯片
文件頁數(shù): 19/128頁
文件大?。?/td> 1382K
代理商: EP7209
EP7209
DS453PP2
19
Oscillator and phase locked loop (PLL) to gen-
erate the core clock speeds of 18.432 MHz,
36.864 MHz, 49.152 MHz, and 73.728 MHz
from an external 3.6864 MHz crystal, with an
alternative external clock input (used in
13 MHz mode).
A low power 32.768 kHz oscillator.
The EP7209 design is optimized for low power dis-
sipation and is fabricated on a fully static
0.25 micron CMOS process. It is available in a
256-ball PBGA or a 208-pin LQFP package.
Figure 2
shows a simplified block diagram of the
EP7209. All external memory and peripheral de-
vices are connected to the 32-bit data bus using the
external 28-bit address bus and control signals.
3.1
The ARM720T consists of an ARM7TDMI 32-bit
RISC processor, a unified cache, and a memory
management unit (MMU). The cache is four-way
set associative with 8-kbytes organized as 512 lines
of 4 words. The cache is directly connected to the
ARM7TDMI, and therefore caches the virtual ad-
dress from the CPU. When the cache misses, the
MMU translates the virtual address into a physical
address. A 64-entry translation lookaside buffer
(TLB) is utilized to speed the address translation
process and reduce bus traffic necessary to read the
page table. The MMU saves power by only trans-
lating the cache misses.
CPU Core
See the ARM720T Data sheet for a complete de-
scription of the various logic blocks that make up
the processor, as well as all internal register infor-
mation.
Figure 2. EP7209 Block Diagram
32.768-KHZ
OSCILLATOR
PLL
INTERRUPT
CONTROLLER
POWER
MANAGEMENT
SSI1 (ADC)
LCD
CONTROLLER
ARM7TDMI
CPU CORE
8-KBYTE
CACHE
MMU
TIMER
COUNTERS (2)
CODEC
ARM720T
INTERNAL DATA BUS
PWM
3.6864 MHZ
32.768 KHZ
EINT[1:3], FIQ,
MEDCHG
BATOK, NEXTPWR
PWRFL, BATCHG
PORTS A, B, D (8-BIT)
PORT E (3-BIT)
KEYBD DRIVERS (0:7)
BUZZER DRIVE
ADCCLK, ADCIN,
ADCOUT, SMPCLK,
ADCCS
SSICLK, SSITXFR,
SSITXDA, SSIRXDA,
SSIRSFR
UART2
IrDA
D[0:31]
NPOR, RUN,
RESET, WAKEUP
EXPCLK, WORD, NCS[0:3],
EXPRDY, WRITE
A[0:27],
DRA[0:12]
LCD DRIVE
LED AND
PHOTODIODE
ASYNC
INTERFACE 1
ASYNC
INTERFACE 2
GPIO
INTERNAL ADDRESS BUS
13-MHZ INPUT
ON-CHIP
BOOT ROM
ON-CHIP SRAM
38,400 BYTES
CL-PS6700
INTFC.
PB[0:1], NCS[4:5]
EXPANSION
CONTROL
UART1
SSI2
EPB BRIDGE
EPB BUS
RTC
FLASHING LED DRIVE
ICE-JTAG
TEST AND
DEVELOPMENT
WRITE
BUFFER
DAI
STATE CONTROL
MEMORY CONTROLLER
LCD
DMA
DC-TO-DC
相關(guān)PDF資料
PDF描述
EP7211 HIGH-PERFORMANCE ULTRA-LOW-POWER SYSTEM-ON-CHIP WITH LCD CONTROLLER
EP7211-CP-A HIGH-PERFORMANCE ULTRA-LOW-POWER SYSTEM-ON-CHIP WITH LCD CONTROLLER
EP7211-CV-A HIGH-PERFORMANCE ULTRA-LOW-POWER SYSTEM-ON-CHIP WITH LCD CONTROLLER
EP7212 HIGH-PERFORMANCE, LOW-POWER SYSTEM-ON-CHIP WITH LCD CONTROLLER AND DIGITAL AUDIO INTERFACE(DAI)
EP7212-CB-A HIGH-PERFORMANCE, LOW-POWER SYSTEM-ON-CHIP WITH LCD CONTROLLER AND DIGITAL AUDIO INTERFACE(DAI)
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