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參數(shù)資料
| 型號： | EP7209 |
| 廠商： | Cirrus Logic, Inc. |
| 英文描述： | Ultra-Low-Power Audio Decoder System-on-Chip |
| 中文描述： | 超低功耗音頻解碼器系統(tǒng)級芯片 |
| 文件頁數(shù)： | 63/128頁 |
| 文件大小： | 1382K |
| 代理商： | EP7209 |
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EP7209
DS453PP2
63
15
CLDFLG
: Cold start flag. This bit will be set if the EP7209 has been reset with a power on reset,
it is cleared by writing to the STFCLR location.
RTCDIV
: This 6-bit field reflects the number of 64 Hz ticks that have passed since the last incre-
ment of the RTC. It is the output of the divide by 64 chain that divides the 64 Hz tick clock down
to 1 Hz for the RTC. The MSB is the 32 Hz output, the LSB is the 1 Hz output.
URXFE1
: UART1 receiver FIFO empty. The meaning of this bit depends on the state of the UFI-
FOEN bit in the UART1 bit rate and line control register. If the FIFO is disabled, this bit will be set
when the RX holding register is empty. If the FIFO is enabled the URXFE bit will be set when the
RX FIFO is empty.
UTXFF1
: UART1 transmit FIFO full. The meaning of this bit depends on the state of the UFI-
FOEN bit in the UART1 bit rate and line control register. If the FIFO is disabled, this bit will be set
when the TX holding register is full. If the FIFO is enabled the UTXFF bit will be set when the TX
FIFO is full.
CRXFE
: Codec RX FIFO empty bit. This will be set if the 16-byte codec RX FIFO is empty.
CTXFF
: Codec TX FIFO full bit. This will be set if the 16-byte codec TX FIFO is full.
SSIBUSY
: Synchronous serial interface busy bit. This bit will be set while data is being shifted in
or out of the synchronous serial interface, when clear data is valid to read.
BOOTBIT0
–
1
: These bits indicate the default (power-on reset) bus width of the ROM interface.
See
Memory Configuration Registers
for more details on the ROM interface bus width. The state
of these bits reflect the state of Port E[0:1] during power on reset, as shown in the table below.
16:21
22
23
24
25
26
27:28
29
30:31
ID
: Will always read
‘
1
’
for the EP7209 device.
VERID
: Version ID bits. These 2 bits determine the version id for the EP7209. Will read
‘
10
’
for
the initial version.
Bit
Description
Table 30. SYSFLG
(cont.)
PE[1]
(BOOTBIT1)
0
0
1
1
PE[0]
(BOOTBIT0)
0
1
0
1
Boot option
32-bit
8-bit
16-bit
Reserved
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| EP7211 | HIGH-PERFORMANCE ULTRA-LOW-POWER SYSTEM-ON-CHIP WITH LCD CONTROLLER |
| EP7211-CP-A | HIGH-PERFORMANCE ULTRA-LOW-POWER SYSTEM-ON-CHIP WITH LCD CONTROLLER |
| EP7211-CV-A | HIGH-PERFORMANCE ULTRA-LOW-POWER SYSTEM-ON-CHIP WITH LCD CONTROLLER |
| EP7212 | HIGH-PERFORMANCE, LOW-POWER SYSTEM-ON-CHIP WITH LCD CONTROLLER AND DIGITAL AUDIO INTERFACE(DAI) |
| EP7212-CB-A | HIGH-PERFORMANCE, LOW-POWER SYSTEM-ON-CHIP WITH LCD CONTROLLER AND DIGITAL AUDIO INTERFACE(DAI) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| EP7209-CB-D | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| EP7209-CV-D | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| EP7211 | 制造商:CIRRUS 制造商全稱:Cirrus Logic 功能描述:HIGH-PERFORMANCE ULTRA-LOW-POWER SYSTEM-ON-CHIP WITH LCD CONTROLLER |
| EP7211(208LQFP) | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Logic IC |
| EP7211(256PBGA) | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Logic IC |
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