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參數(shù)資料
| 型號： | EP7209 |
| 廠商： | Cirrus Logic, Inc. |
| 英文描述： | Ultra-Low-Power Audio Decoder System-on-Chip |
| 中文描述： | 超低功耗音頻解碼器系統(tǒng)級芯片 |
| 文件頁數(shù)： | 14/128頁 |
| 文件大小： | 1382K |
| 代理商： | EP7209 |
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EP7209
14
DS453PP2
Interrupts
nMEDCHG/
nBROM
I
Media changed input; active low, deglitched. Used as a general purpose FIQ
interrupt during normal operation. It is also used on power up to configure the
processor to either boot from the internal Boot ROM, or from external memory.
When low, the chip will boot from the internal Boot ROM.
External active low fast interrupt request input
External active high interrupt request input
Two general purpose, active low interrupt inputs
Power fail input; active low, deglitched input to force system into the Standby
State
Main battery OK input; falling edge generates a FIQ, a low level in the Standby
State inhibits system start up; deglitched input
External power sense; must be driven low if the system is powered by an
external source
New battery sense; driven low if battery voltage falls below the "no-battery"
threshold; it is a deglitched input
Power-on reset input. This signal is not deglitched. When active it completely
resets the entire system, including all the RTC registers. Upon power-up, the
signal must be held active low for a minimum of 100
μ
sec after Vdd has set-
tled. During normal operation, nPOR needs to be held low for at least one
clock cycle of the selected clock speed (i.e., when running at 13 MHz, the
pulse width of nPOR needs to be > 77 nsec).
nEXTFIQ
EINT[3]
nEINT[1:2]
I
I
I
Power
Management
nPWRFL
1
I
BATOK
1
I
nEXTPWR
I
nBATCHG
1
I
State Control
nPOR
I
Note that nURESET, RUN/CLKEN, TEST(0), TEST(1), PE(0), PE(1), PE(2),
DRIVE(0), DRIVE(1), DD(0), DD(1), DD(2), and DD(3) are all latched on rising
edge of nPOR.
This pin is programmed to either output the RUN signal or the CLKEN signal.
The CLKENSL bit is used to configure this pin. When RUN is selected, the pin
will be high when the system is active or idle, low while in the Standby State.
When CLKEN is selected, the pin will only be driven low when in the Standby
State (For RUN, see
Table 6
).
Wake up deglitched input signal; rising edge forces system into the Operating
State from the Standby State; active after an nPOR reset. The wakeup signal
can not be used to exit Idle, only Standby. Wakeup must wait at least 2 sec-
onds before it goes high for it to be detected by the CPU. It must also be held
high for at least 125
μ
sec to guarantee its detection. Toggling wakeup after its
first detection has no effect (i.e., it is ignored).
User reset input; active low deglitched input from user reset button.
This pin is also latched upon the rising edge of nPOR and read along with the
input pins nTEST[0:1] to force the device into special test modes. nURESET
does not reset the RTC.
DAI/Codec/SSI2 clock signal
DAI/Codec/SSI2 serial data output frame/synchronization pulse output
DAI/Codec/SSI2 serial data output
DAI/Codec/SSI2 serial data input
RUN/CLKEN
I/O
WAKEUP
1
I
nURESET
1
I
DAI, Codec or
SSI2
Interface
(See
Table 5
for
SSI2/Codec/DAI
Pin Multiplexing)
SSICLK
SSITXFR
SSITXDA
I/O
I/O
O
SSIRXDA
I
SSIRXFR
I/O
SSI2 serial data input frame/synchronization pulse
DAI external clock input
Function
Signal
Name
Signal
Description
Table 4. External Signal Functions
(cont.)
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