SSPSTAT: MSSP STATUS REGISTER (I
參數(shù)資料
型號(hào)： ENC624J600T-I/PT
廠商： Microchip Technology
文件頁數(shù)： 76/168頁
文件大?。?/td> 0K
描述： IC ETHERNET CTRLR W/SPI 64-TQFP
視頻文件： Fast 100 Mbps Ethernet PICtail Plus Overview
標(biāo)準(zhǔn)包裝： 1,200
控制器類型： 以太網(wǎng)控制器（IEEE 802.3）
接口： SPI
電源電壓： 3 V ~ 3.6 V
電流 - 電源： 96mA
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 64-TQFP
供應(yīng)商設(shè)備封裝： 64-TQFP（10x10）
包裝： 帶卷 (TR)
配用： AC164132-ND - BOARD DAUGHTER PICTAIL ETHERNET
2007 Microchip Technology Inc.
DS39599G-page 165
PIC18F2220/2320/4220/4320
REGISTER 17-3:
SSPSTAT: MSSP STATUS REGISTER (I2C MODE)
R/W-0
R-0
SMP
CKE
D/A
P(1)
S(2)
R/W
UA
BF
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
SMP: Slew Rate Control bit
In Master or Slave mode:
1 = Slew rate control disabled
0 = Slew rate control enabled
bit 6
CKE: SMBus Select bit
In Master or Slave mode:
1 = Enable SMBus specific inputs
0 = Disable SMBus specific inputs
bit 5
D/A: Data/Address bit
In Master mode:
Reserved.
In Slave mode:
1 = Indicates that the last byte received or transmitted was data
0 = Indicates that the last byte received or transmitted was address
bit 4
P: Stop bit(1)
1 = Indicates that a Stop bit has been detected last
0 = Stop bit was not detected last
bit 3
S: Start bit(2)
1 = Indicates that a Start bit has been detected last
0 = Start bit was not detected last
bit 2
R/W: Read/Write bit Information (I2C mode only)
In Slave mode:(3)
1 = Read
0 = Write
In Master mode:(4)
1 = Transmit is in progress
0 = Transmit is not in progress
bit 1
UA: Update Address bit (10-Bit Slave mode only)
1 = Indicates that the user needs to update the address in the SSPADD register
0 = Address does not need to be updated
bit 0
BF: Buffer Full Status bit
In Transmit mode:
1 = Data transmit in progress (does not include the ACK and Stop bits), SSPBUF is full
0 = Data transmit complete (does not include the ACK and Stop bits), SSPBUF is empty
In Receive mode:
1 = Receive complete, SSPBUF is full
0 = Receive not complete, SSPBUF is empty
Note 1:
This bit is cleared on Reset when SSPEN is cleared or a Start bit has been detected.
2:
This bit is cleared on Reset when SSPEN is cleared or a Stop bit has been detected.
3:
This bit holds the R/W bit information following the last address match. This bit is only valid from the
address match to the next Start bit, Stop bit or not ACK bit.
4:
ORing this bit with the SSPCON2 bits, SEN, RSEN, PEN, RCEN or ACKEN will indicate if the MSSP is in
Idle mode.
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