There are two memory blocks in each of these PIC
參數(shù)資料
型號： ENC624J600T-I/PT
廠商： Microchip Technology
文件頁數(shù)： 57/168頁
文件大小： 0K
描述： IC ETHERNET CTRLR W/SPI 64-TQFP
視頻文件： Fast 100 Mbps Ethernet PICtail Plus Overview
標準包裝： 1,200
控制器類型： 以太網(wǎng)控制器（IEEE 802.3）
接口： SPI
電源電壓： 3 V ~ 3.6 V
電流 - 電源： 96mA
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 64-TQFP
供應商設備封裝： 64-TQFP（10x10）
包裝： 帶卷 (TR)
配用： AC164132-ND - BOARD DAUGHTER PICTAIL ETHERNET
2007 Microchip Technology Inc.
DS21993C-page 13
PIC16CR7X
2.0
MEMORY ORGANIZATION
There are two memory blocks in each of these PIC
MCUs. The Program Memory and Data Memory have
separate buses so that concurrent access can occur
and is detailed in this section. The Program Memory
can be read internally by user code (see Section 3.0
Additional information on device memory may be found
in the “PIC Mid-Range MCU Family Reference
Manual” (DS33023).
2.1
Program Memory Organization
The PIC16CR7X devices have a 13-bit program
counter capable of addressing an 8K word x 14-bit pro-
gram memory space. The PIC16CR77/76 devices
have 8K words of ROM program memory and the
PIC16CR73/74 devices have 4K words. The program
memory maps for PIC16CR7X devices are shown in
Figure 2-1. Accessing a location above the physically
implemented address will cause a wraparound.
The Reset vector is at 0000h and the interrupt vector is
at 0004h.
2.2
Data Memory Organization
The Data Memory is partitioned into multiple banks,
which contain the General Purpose Registers (GPR)
and the Special Function Registers (SFR). Bits RP1
(STATUS<6>) and RP0 (STATUS<5>) are the bank
select bits:
Each bank extends up to 7Fh (128 bytes). The lower
locations of each bank are reserved for the Special
Function Registers. Above the Special Function Regis-
ters are General Purpose Registers, implemented as
static RAM. All implemented banks contain Special
Function Registers. Some frequently used Special
Function Registers from one bank may be mirrored in
another bank for code reduction and quicker access.
2.2.1
GENERAL PURPOSE REGISTER
FILE
The register file (shown in Figure 2-2 and Figure 2-3)
can be accessed either directly, or indirectly, through
the File Select Register (FSR).
FIGURE 2-1:
PROGRAM MEMORY MAPS AND STACKS FOR PIC16CR7X DEVICES
RP1:RP0
Bank
00
0
01
1
10
2
11
3
PC<12:0>
13
0000h
0004h
0005h
Stack Level 1
Stack Level 8
Reset Vector
Interrupt Vector
On-Chip
CALL, RETURN
RETFIE, RETLW
1FFFh
Stack Level 2
Program
Memory
Page 0
Page 1
07FFh
0800h
0FFFh
1000h
17FFh
1800h
Reset Vector
Interrupt Vector
Page 0
Page 1
Page 2
Page 3
0000h
0004h
0005h
1FFFh
07FFh
0800h
0FFFh
1000h
PC<12:0>
13
Stack Level 1
Stack Level 8
CALL, RETURN
RETFIE, RETLW
Stack Level 2
Unimplemented
Read as ‘0’
On-Chip
Program
Memory
PIC16CR76/77
PIC16CR73/74
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