參數(shù)資料
型號： ENC624J600T-I/PT
廠商： Microchip Technology
文件頁數(shù)： 111/168頁
文件大?。?/td> 0K
描述： IC ETHERNET CTRLR W/SPI 64-TQFP
視頻文件： Fast 100 Mbps Ethernet PICtail Plus Overview
標準包裝： 1,200
控制器類型： 以太網(wǎng)控制器（IEEE 802.3）
接口： SPI
電源電壓： 3 V ~ 3.6 V
電流 - 電源： 96mA
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 64-TQFP
供應(yīng)商設(shè)備封裝： 64-TQFP（10x10）
包裝： 帶卷 (TR)
配用： AC164132-ND - BOARD DAUGHTER PICTAIL ETHERNET
2007 Microchip Technology Inc.
DS21993C-page 45
PIC16CR7X
5.3
Prescaler
There is only one prescaler available on the microcon-
troller; it is shared exclusively between the Timer0 mod-
ule and the Watchdog Timer. The usage of the prescaler
is also mutually exclusive: that is, a prescaler assign-
ment for the Timer0 module means that there is no pres-
caler for the Watchdog Timer, and vice versa. This
prescaler is not readable or writable (see Figure 5-1).
The PSA and PS2:PS0 bits (OPTION_REG<3:0>)
determine the prescaler assignment and prescale ratio.
Examples of code for assigning the prescaler assign-
ment are shown in Example 5-1 and Example 5-2.
Note that when the prescaler is being assigned to the
WDT with ratios other than 1:1, lines 2 and 3 (high-
lighted) are optional. If a prescale ratio of 1:1 is used,
however, these lines must be used to set a temporary
value. The final 1:1 value is then set in lines 10 and 11
(highlighted). (Line numbers are included in the
example for illustrative purposes only, and are not part
of the actual code.)
When assigned to the Timer0 module, all instructions
writing to the TMR0 register (e.g. CLRF 1, MOVWF 1,
BSF 1,x
....etc.) will clear the prescaler. When assigned
to WDT, a CLRWDT instruction will clear the prescaler
along with the Watchdog Timer.
EXAMPLE 5-1:
CHANGING THE PRESCALER ASSIGNMENT FROM TIMER0 TO WDT
EXAMPLE 5-2:
CHANGING THE PRESCALER ASSIGNMENT FROM WDT TO TIMER0
TABLE 5-1:
REGISTERS ASSOCIATED WITH TIMER0
Note:
Writing to TMR0 when the prescaler is
assigned to Timer0 will clear the prescaler
count, but will not change the prescaler
assignment.
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR,
BOR
Value on
all other
Resets
01h,101h
TMR0
Timer0 Module Register
xxxx xxxx
uuuu uuuu
0Bh,8Bh,
10Bh,18Bh
INTCON
GIE
PEIE
TMR0IE
INTE
RBIE
TMR0IF
INTF
RBIF
0000 000x
0000 000u
81h,181h
OPTION_REG RBPU INTEDG
T0CS
T0SE
PSA
PS2
PS1
PS0
1111 1111
Legend:
x
= unknown, u = unchanged,
– = unimplemented locations read as ‘0’. Shaded cells are not used by Timer0.
1)
BSF
STATUS, RP0
; Bank1
2)
MOVLW
b’xx0x0xxx’
; Select clock source and prescale value of
3)
MOVWF
OPTION_REG
; other than 1:1
4)
BCF
STATUS, RP0
; Bank0
5)
CLRF
TMR0
; Clear TMR0 and prescaler
6)
BSF
STATUS, RP1
; Bank1
7)
MOVLW
b’xxxx1xxx’
; Select WDT, do not change prescale value
8)
MOVWF
OPTION_REG
9)
CLRWDT
; Clears WDT and prescaler
10) MOVLW
b’xxxx1xxx’
; Select new prescale value and WDT
11) MOVWF
OPTION_REG
12) BCF
STATUS, RP0
; Bank0
CLRWDT
; Clear WDT and prescaler
BSF
STATUS, RP0
; Bank1
MOVLW
b’xxxx0xxx’
; Select TMR0, new prescale
MOVWF
OPTION_REG
; value and clock source
BCF
STATUS, RP0
; Bank0
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