參數(shù)資料
型號(hào)： ENC624J600T-I/PT
廠商： Microchip Technology
文件頁數(shù)： 123/168頁
文件大?。?/td> 0K
描述： IC ETHERNET CTRLR W/SPI 64-TQFP
視頻文件： Fast 100 Mbps Ethernet PICtail Plus Overview
標(biāo)準(zhǔn)包裝： 1,200
控制器類型： 以太網(wǎng)控制器（IEEE 802.3）
接口： SPI
電源電壓： 3 V ~ 3.6 V
電流 - 電源： 96mA
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 64-TQFP
供應(yīng)商設(shè)備封裝： 64-TQFP（10x10）
包裝： 帶卷 (TR)
配用： AC164132-ND - BOARD DAUGHTER PICTAIL ETHERNET
PIC16CR7X
DS21993C-page 56
2007 Microchip Technology Inc.
8.4.1
CCP PIN CONFIGURATION
The user must configure the RC2/CCP1 pin as an
output by clearing the TRISC<2> bit.
8.4.2
TIMER1 MODE SELECTION
Timer1 must be running in Timer mode or Synchro-
nized Counter mode if the CCP module is using the
compare feature. In Asynchronous Counter mode, the
compare operation may not work.
8.4.3
SOFTWARE INTERRUPT MODE
When Generate Software Interrupt mode is chosen, the
CCP1 pin is not affected. The CCP1IF or CCP2IF bit is
set, causing a CCP interrupt (if enabled).
8.4.4
SPECIAL EVENT TRIGGER
In this mode, an internal hardware trigger is generated,
which may be used to initiate an action.
The special event trigger output of CCP1 resets the
TMR1 register pair. This allows the CCPR1 register to
effectively be a 16-bit programmable period register for
Timer1.
The special event trigger output of CCP2 resets the
TMR1 register pair and starts an A/D conversion (if the
A/D module is enabled).
TABLE 8-3:
REGISTERS ASSOCIATED WITH CAPTURE, COMPARE AND TIMER1
Note:
Clearing the CCP1CON register will force
the RC2/CCP1 compare output latch to
the default low level. This is not the
PORTC
I/O data latch.
Note:
The special event trigger from the CCP1
and CCP2 modules will not set interrupt
flag bit TMR1IF (PIR1<0>).
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR,
BOR
Value on
all other
Resets
0Bh,8Bh,
10Bh,18Bh
INTCON
GIE
PEIE
TMR0IE
INTE
RBIE
TMR0IF
INTF
RBIF
0000 000x 0000 000u
0Ch
PIR1
PSPIF(1)
ADIF
RCIF
TXIF
SSPIF
CCP1IF
TMR2IF
TMR1IF 0000 0000 0000 0000
0Dh
PIR2
—
—CCP2IF ---- ---0 ---- ---0
8Ch
PIE1
PSPIE(1)
ADIE
RCIE
TXIE
SSPIE
CCP1IE
TMR2IE
TMR1IE 0000 0000 0000 0000
8Dh
PIE2
—
—CCP2IE ---- ---0 ---- ---0
87h
TRISC
PORTC Data Direction Register
1111 1111 1111 1111
0Eh
TMR1L
Holding Register for the Least Significant Byte of the 16-bit TMR1 Register
xxxx xxxx uuuu uuuu
0Fh
TMR1H
Holding Register for the Most Significant Byte of the 16-bit TMR1 Register
xxxx xxxx uuuu uuuu
10h
T1CON
—
T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON --00 0000 --uu uuuu
15h
CCPR1L
Capture/Compare/PWM Register 1 (LSB)
xxxx xxxx uuuu uuuu
16h
CCPR1H
Capture/Compare/PWM Register 1 (MSB)
xxxx xxxx uuuu uuuu
17h
CCP1CON
—
CCP1X
CCP1Y
CCP1M3
CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000
1Bh
CCPR2L
Capture/Compare/PWM Register 2 (LSB)
xxxx xxxx uuuu uuuu
1Ch
CCPR2H
Capture/Compare/PWM Register 2 (MSB)
xxxx xxxx uuuu uuuu
1Dh
CCP2CON
—
CCP2X
CCP2Y
CCP2M3
CCP2M2 CCP2M1 CCP2M0 --00 0000 --00 0000
Legend:
x
= unknown, u = unchanged, – = unimplemented, read as ‘0’. Shaded cells are not used by Capture and Timer1.
Note
1:
The PSP is not implemented on the PIC16CR73/76; always maintain these bits clear.
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