參數(shù)資料
型號： ENC624J600T-I/PT
廠商： Microchip Technology
文件頁數(shù)： 74/168頁
文件大小： 0K
描述： IC ETHERNET CTRLR W/SPI 64-TQFP
視頻文件： Fast 100 Mbps Ethernet PICtail Plus Overview
標準包裝： 1,200
控制器類型： 以太網控制器（IEEE 802.3）
接口： SPI
電源電壓： 3 V ~ 3.6 V
電流 - 電源： 96mA
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 64-TQFP
供應商設備封裝： 64-TQFP（10x10）
包裝： 帶卷 (TR)
配用： AC164132-ND - BOARD DAUGHTER PICTAIL ETHERNET
2007 Microchip Technology Inc.
DS39599G-page 163
PIC18F2220/2320/4220/4320
17.3.8
MASTER IN POWER-MANAGED
MODES
In Master mode, module clocks may be operating at a
different speed than when in full-power mode, or in the
case of the power-managed Sleep mode, all clocks are
halted.
In most power-managed modes, a clock is provided
to the peripherals and is derived from the primary
clock source, the secondary clock (Timer1 oscillator
at 32.768 kHz) or the internal oscillator block (one of
eight frequencies between 31 kHz and 8 MHz). See
Switching” for additional information.
In most cases, the speed that the master clocks SPI
data is not important; however, this should be
evaluated for each system.
If MSSP interrupts are enabled, they can wake the con-
troller from a power-managed mode when the master
completes sending data. If an exit from a power-
managed mode is not desired, MSSP interrupts should
be disabled.
If the Sleep mode is selected, all module clocks are
halted and the transmission/reception will pause until
the device wakes from the power-managed mode.
After the device returns to full-power mode, the module
will resume transmitting and receiving data.
17.3.8.1
Slave in Power-Managed Modes
In Slave mode, the SPI Transmit/Receive Shift register
operates asynchronously to the device. This allows the
device to be placed in any power-managed mode and
data to be shifted into the SPI Transmit/Receive Shift
register. When all 8 bits have been received, the MSSP
interrupt flag bit will be set and if MSSP interrupts are
enabled, will wake the device from a power-managed
mode.
17.3.9
EFFECTS OF A RESET
A Reset disables the MSSP module and terminates the
current transfer.
17.3.10
BUS MODE COMPATIBILITY
Table 17-1 shows the compatibility between the
standard SPI modes and the states of the CKP and
CKE control bits.
TABLE 17-1:
SPI BUS MODES
There is also an SMP bit which controls when the data
is sampled.
TABLE 17-2:
REGISTERS ASSOCIATED WITH SPI OPERATION
Standard SPI Mode
Terminology
Control Bits State
CKP
CKE
0, 0
0
1
0, 1
0
1, 0
1
1, 1
1
0
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Value on
all other
Resets
INTCON
GIE/GIEH
PEIE/
GIEL
TMR0IE
INT0IE
RBIE
TMR0IF
INT0IF
RBIF
0000 000x 0000 000u
PIR1
PSPIF(1)
ADIF
RCIF
TXIF
SSPIF
CCP1IF
TMR2IF
TMR1IF
0000 0000 0000 0000
PIE1
PSPIE(1)
ADIE
RCIE
TXIE
SSPIE
CCP1IE
TMR2IE
TMR1IE
0000 0000 0000 0000
IPR1
PSPIP(1)
ADIP
RCIP
TXIP
SSPIP
CCP1IP
TMR2IP
TMR1IP
1111 1111 1111 1111
TRISC
PORTC Data Direction Register
1111 1111 1111 1111
SSPBUF
MSSP Receive Buffer/Transmit Register
xxxx xxxx uuuu uuuu
SSPCON1
WCOL
SSPOV
SSPEN
CKP
SSPM3
SSPM2
SSPM1
SSPM0
0000 0000 0000 0000
TRISA
TRISA7(1) TRISA6(1) PORTA Data Direction Register
--11 1111 --11 1111
SSPSTAT
SMP
CKE
D/A
P
S
R/W
UA
BF
0000 0000 0000 0000
Legend: x = unknown, u = unchanged, - = unimplemented, read as ‘0’. Shaded cells are not used by the MSSP in SPI mode.
Note 1: The PSPIF, PSPIE and PSPIP bits are reserved on the PIC18F2X20 devices; always maintain these bits clear.
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