參數(shù)資料
型號： ENC624J600T-I/PT
廠商： Microchip Technology
文件頁數(shù)： 44/168頁
文件大?。?/td> 0K
描述： IC ETHERNET CTRLR W/SPI 64-TQFP
視頻文件： Fast 100 Mbps Ethernet PICtail Plus Overview
標(biāo)準(zhǔn)包裝： 1,200
控制器類型： 以太網(wǎng)控制器（IEEE 802.3）
接口： SPI
電源電壓： 3 V ~ 3.6 V
電流 - 電源： 96mA
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 64-TQFP
供應(yīng)商設(shè)備封裝： 64-TQFP（10x10）
包裝： 帶卷 (TR)
配用： AC164132-ND - BOARD DAUGHTER PICTAIL ETHERNET
PIC18F2220/2320/4220/4320
DS39599G-page 136
2007 Microchip Technology Inc.
15.4
Compare Mode
In Compare mode, the 16-bit CCPR1 (CCPR2) register
value is constantly compared against either the
TMR1 register pair value, or the TMR3 register pair
value. When a match occurs, the RC2/CCP1/P1A
(RC1/T1OSI/CCP2) pin:
Is driven high
Is driven low
Toggles output (high-to-low or low-to-high)
Remains unchanged (interrupt only)
The action on the pin is based on the value of control
bits, CCP1M3:CCP1M0 (CCP2M3:CCP2M0). At the
same time, interrupt flag bit, CCP1IF (CCP2IF), is set.
15.4.1
CCP PIN CONFIGURATION
The user must configure the CCPx pin as an output by
clearing the appropriate TRISC bit.
15.4.2
TIMER1/TIMER3 MODE SELECTION
Timer1 and/or Timer3 must be running in Timer mode,
or Synchronized Counter mode, if the CCP module is
using the compare feature. In Asynchronous Counter
mode, the compare operation may not work.
15.4.3
SOFTWARE INTERRUPT MODE
When generate software interrupt is chosen, the CCP1
pin is not affected. Only a CCP interrupt is generated (if
enabled).
15.4.4
SPECIAL EVENT TRIGGER
In this mode, an internal hardware trigger is generated
which may be used to initiate an action.
The Special Event Trigger output of CCP1 resets the
TMR1 register pair. This allows the CCPR1 register to
effectively be a 16-bit programmable Period register for
Timer1.
The special trigger output of CCP2 resets either the
TMR1 or TMR3 register pair. Additionally, the CCP2
Special Event Trigger will start an A/D conversion if the
A/D module is enabled.
FIGURE 15-2:
COMPARE MODE OPERATION BLOCK DIAGRAM
Note:
Clearing the CCP1CON register will force
the RC2/CCP1/P1A compare output latch
to the default low level. This is not the
PORTC I/O data latch.
Note:
The Special Event Trigger from the CCP2
module will not set the Timer1 or Timer3
interrupt flag bits.
CCPR1H CCPR1L
TMR1H
TMR1L
Comparator
QS
R
Output
Logic
Special Event Trigger
Set Flag bit CCP1IF
Match
RC2/CCP1/P1A
TRISC<2>
CCP1CON<3:0>
Mode Select
Output Enable
Special Event Trigger will:
Reset Timer1 or Timer3 but not set Timer1 or Timer3 interrupt flag bit
and set bit GO/DONE (ADCON0<2>) which starts an A/D conversion (CCP2 only)
TMR3H
TMR3L
T3CCP2
CCPR2H CCPR2L
Comparator
1
0
T3CCP2
T3CCP1
QS
R
Output
Logic
Special Event Trigger
Set Flag bit CCP2IF
Match
RC1/T1OSI/CCP2
TRISC<1>
CCP2CON<3:0>
Mode Select
Output Enable
01
pin
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