參數(shù)資料
型號(hào)： ENC624J600T-I/PT
廠商： Microchip Technology
文件頁數(shù)： 43/168頁
文件大?。?/td> 0K
描述： IC ETHERNET CTRLR W/SPI 64-TQFP
視頻文件： Fast 100 Mbps Ethernet PICtail Plus Overview
標(biāo)準(zhǔn)包裝： 1,200
控制器類型： 以太網(wǎng)控制器（IEEE 802.3）
接口： SPI
電源電壓： 3 V ~ 3.6 V
電流 - 電源： 96mA
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 64-TQFP
供應(yīng)商設(shè)備封裝： 64-TQFP（10x10）
包裝： 帶卷 (TR)
配用： AC164132-ND - BOARD DAUGHTER PICTAIL ETHERNET
2007 Microchip Technology Inc.
DS39599G-page 135
PIC18F2220/2320/4220/4320
15.3
Capture Mode
In Capture mode, CCPR1H:CCPR1L captures the 16-bit
value of the TMR1 or TMR3 registers when an event
occurs on pin RC2/CCP1/P1A. An event is defined as
one of the following:
every falling edge
every rising edge
every 4th rising edge
every 16th rising edge
The event is selected by control bits, CCP1M3:CCP1M0
(CCP1CON<3:0>). When a capture is made, the inter-
rupt request flag bit, CCP1IF (PIR1<2>), is set; it must
be cleared in software. If another capture occurs before
the value in register CCPR1 is read, the old captured
value is overwritten by the new captured value.
15.3.1
CCP PIN CONFIGURATION
In Capture mode, the RC2/CCP1/P1A pin should be
configured as an input by setting the TRISC<2> bit.
15.3.2
TIMER1/TIMER3 MODE SELECTION
The timers that are to be used with the capture feature
(either Timer1 and/or Timer3) must be running in Timer
mode or Synchronized Counter mode. In Asynchro-
nous Counter mode, the capture operation may not
work. The timer to be used with each CCP module is
selected in the T3CON register.
15.3.3
SOFTWARE INTERRUPT
When the Capture mode is changed, a false capture
interrupt may be generated. The user should keep bit
CCP1IE (PIE1<2>) clear to avoid false interrupts and
should clear the flag bit, CCP1IF, following any such
change in operating mode.
15.3.4
CCP PRESCALER
There are four prescaler settings specified by bits
CCP1M3:CCP1M0. Whenever the CCP module is
turned off, or the CCP module is not in Capture mode,
the prescaler counter is cleared. This means that any
Reset will clear the prescaler counter.
Switching from one capture prescaler to another may
generate an interrupt. Also, the prescaler counter will
not be cleared, therefore, the first capture may be from
a non-zero prescaler. Example 15-1 shows the recom-
mended method for switching between capture
prescalers. This example also clears the prescaler
counter and will not generate the “false” interrupt.
EXAMPLE 15-1:
CHANGING BETWEEN
CAPTURE PRESCALERS
FIGURE 15-1:
CAPTURE MODE OPERATION BLOCK DIAGRAM
Note:
If the RC2/CCP1/P1A is configured as an
output, a write to the port can cause a
capture condition.
CLRF
CCP1CON, F
; Turn CCP module off
MOVLW
NEW_CAPT_PS
; Load WREG with the
; new prescaler mode
; value and CCP ON
MOVWF
CCP1CON
; Load CCP1CON with
; this value
CCPR1H
CCPR1L
TMR1H
TMR1L
Set Flag bit CCP1IF
TMR3
Enable
Q’s
CCP1CON<3:0>
CCP1 pin
Prescaler
÷ 1, 4, 16
and
Edge Detect
TMR3H
TMR3L
TMR1
Enable
T3CCP2
CCPR2H
CCPR2L
TMR1H
TMR1L
Set Flag bit CCP2IF
TMR3
Enable
Q’s
CCP2CON<3:0>
CCP2 pin
Prescaler
÷ 1, 4, 16
and
Edge Detect
TMR3H
TMR3L
TMR1
Enable
T3CCP2
T3CCP1
T3CCP2
T3CCP1
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