參數(shù)資料
型號(hào): DSP56600
廠商: 飛思卡爾半導(dǎo)體(中國(guó))有限公司
英文描述: Implementing Viterbi Decoders Using the VSL Instruction on DSP Families
中文描述: 維特比解碼器實(shí)現(xiàn)上使用DSP的家庭教學(xué)的VSL
文件頁(yè)數(shù): 97/108頁(yè)
文件大?。?/td> 726K
代理商: DSP56600
24-Bit Algorithm Program Listing
Viterbi Decoder Implementation
For More Information On This Product,
Go to: www.freescale.com
C-5
;*****************************************************************************
;
AT this point, X is configured with br 11|00, y with 00|11, and
;
AB with 01|10, BA with 10|01 all needed for quick storage in XY memory
;*****************************************************************************
move
move
move
move
move
move
move
move
move
move
move
move
move
move
move
move
endm
x,l:(r2)+
ab,l:(r2)+
ba,l:(r2)+
y,l:(r2)+
y,l:(r2)+
ba,l:(r2)+
ab,l:(r2)+
x,l:(r2)+
ba,l:(r2)+
y,l:(r2)+
x,l:(r2)+
ab,l:(r2)+
ab,l:(r2)+
x,l:(r2)+
y,l:(r2)+
ba,l:(r2)+
;store 11 in location 0.
;store 01 in location 1
;store 10 in location 2
;store 00 in location 3
;store 00 in location 4
;store 10 in location 5
;store 01 in location 6
;store 11 in location 7
;store 10 in location 8
;store 00 in location 9
;store 11 in location 10
;store 01 in location 11
;store 01 in location 12
;store 11 in location 13
;store 00 in location 14
;store 10 in location 15 r2-> BRX
Example C-1
24-bit Algorithm Program Listing (Continued)
F
Freescale Semiconductor, Inc.
n
.
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