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參數(shù)資料
| 型號： | DSP56600 |
| 廠商： | 飛思卡爾半導(dǎo)體(中國)有限公司 |
| 英文描述： | Implementing Viterbi Decoders Using the VSL Instruction on DSP Families |
| 中文描述： | 維特比解碼器實現(xiàn)上使用DSP的家庭教學(xué)的VSL |
| 文件頁數(shù)： | 28/108頁 |
| 文件大?。?/td> | 726K |
| 代理商： | DSP56600 |
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2-14
Viterbi Decoder Implementation
For More Information On This Product,
Go to: www.freescale.com
The Viterbi Algorithm
Algorithmic Enhancements
Figure 2-9
Applying an Offset to Obtain Odd Symmetry in the Branch Metrics
A second modification to the algorithm is the ability to use soft decisions. By this we
mean that the input data need not be just a 0/1 decision on a receiver statistic. We can
assign intermediate values to indicate the reliability of the decision. In this way, a 0.001
can be a very reliable 0, a .75 can be a moderately reliable one, and a .49 is just barely a
zero. The Viterbi algorithm generalizes to handle soft decisions with no trouble; the
additions for the metric updates simply have more bits. By using soft decisions, the
ability of the decoder to correct errors is greatly improved.
Note that from an implementation on our DSP view, this modification is almost
invisible, as 16-bit or 24-bit arithmetic will be done regardless of the number of bits in the
branch metrics. Of course, provisions to protect path metric values from overflow
may
have to change for some systems.
00100
10100
01000
01001
11
00/-1
11/1
Decoder
input
S
1
S
0
S
2
S
3
S
4
1
1
D
D
2
D
3
D
4
D
5
00100
10100
01000
01001
S
1
S
0
S
2
S
3
S
4
1
D
D
2
D
3
D
4
D
5
11/1
00/-1
After subtracting
one from each
branch metric, the
updates can be
be done by adding
and subtracting 1.
Similarly, the lower
state update can be
done by subtracting 1
first, then adding 1
for the lower branch.
Same metric, but the
add/sub order is
reversed.
F
Freescale Semiconductor, Inc.
n
.
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