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參數(shù)資料
| 型號： | DSP56600 |
| 廠商： | 飛思卡爾半導(dǎo)體(中國)有限公司 |
| 英文描述： | Implementing Viterbi Decoders Using the VSL Instruction on DSP Families |
| 中文描述： | 維特比解碼器實(shí)現(xiàn)上使用DSP的家庭教學(xué)的VSL |
| 文件頁數(shù)： | 18/108頁 |
| 文件大?。?/td> | 726K |
| 代理商： | DSP56600 |
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2-4
Viterbi Decoder Implementation
For More Information On This Product,
Go to: www.freescale.com
The Viterbi Algorithm
Viterbi Decoder
Error correcting codes have some standard notation. This example, used in the wireless
standard IS-136, is a rate 1/2 code, meaning that for each processing period, one
information bit is taken in and two bits of output are generated. The word (S
is the encoder state. The remaining bit of the encoder we call the input bit. There is a
convenient notation that describes the encoder using polynomials. This encoder can be
described with the encoding polynomials (1+D+D
corresponds to a one clock delay for that adder input. Given the encoding polynomials,
we can begin to design the Viterbi decoder.
4
,S
3
,S
2
,S
1
,S
0
)
3
+D
5
,1+D
2
+D
3
+D
4
+D
5
). Each factor D
2.3
VITERBI DECODER
To design a Viterbi decoder, begin by taking some example encoder input and
generating the corresponding output. An example appears in
assumed that the encoder is 0 filled at the start. For proper decoding, we need to recreate
the encoder states and find the set of state changes, or transitions, that produce an
encoder output that best agrees with our decoder input data. We begin using the same
assumption we used in generating the encoder output in
initial state of the encoder is 00000.
Table 2-1
, where it is
Table 2-1
. We assume that the
Table 2-1
Input/Output Mapping
To compare our recreated encoder state with the decoder input, we keep track of the
agreements between the recreated encoder outputs and the decoder inputs. The
cumulative agreement for a path leading to one particular recreated encoder state is
called a path metric for that path. Incremental agreements are called branch metrics.
Encoder
Input
Encoder
Output
1
11
0
10
1
10
1
10
0
10
F
Freescale Semiconductor, Inc.
n
.
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