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參數(shù)資料
| 型號： | DSP56600 |
| 廠商： | 飛思卡爾半導(dǎo)體(中國)有限公司 |
| 英文描述： | Implementing Viterbi Decoders Using the VSL Instruction on DSP Families |
| 中文描述： | 維特比解碼器實現(xiàn)上使用DSP的家庭教學(xué)的VSL |
| 文件頁數(shù)： | 31/108頁 |
| 文件大?。?/td> | 726K |
| 代理商： | DSP56600 |
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Expanding the Viterbi Algorithm
Introduction
Viterbi Decoder Implementation
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3-3
3.1
INTRODUCTION
Having introduced the principal concepts involved in the Viterbi algorithm, we can
proceed to generate code to implement it. There are, however, a number of details that
need attention. We have concentrated on the Viterbi butterfly.The next step involves,
among other things, generating the branch metrics and allowing for multiple word
traceback to recover the output data. Up to now, we have not even discussed how the
path decision might be stored.
The example code in this section shows a basic implementation of the Viterbi algorithm
implemented on the DSP56600 assembly language. These examples decode data
encoded using the convolutional code for IS-136.
3.2
PARTITIONING THE TASK
In this section, we develop code to implement the entire algorithm. We will start with
the most critical section, the Viterbi butterfly code. We then work outward, developing
branch metric storage code and traceback instructions.
All code assumes 16-bit registers and will run as-is on the DSP56600 DSP family. It also
runs correctly on the DSP56300 family of DSPs when they are set in 16-bit arithmetic
mode.
A complete code listing of the modules presented here appears in
Appendix A
. The code
can be easily modified for 24-bit operation by changing one line of code, as shown in the
detailed traceback code discussion. Note that the test data provided is 16-bit data, and
would have to be changed to 24-bit data to test correctly in 24-bit arithmetic mode. Also,
Appendix C
has a 24-bit version of the code discussed in
Section 4
.
3.3
THE INNER LOOP: VITERBI BUTTERFLIES
We begin by discussing the code used to do a Viterbi butterfly (updating the states). The
easiest way to present the code for this section is to display the instructions, then discuss
their function. The code utilizes the Viterbi shift left (VSL) instruction, designed for
DSP56300 and DSP56600 DSP families to enhance their ability to execute the Viterbi
algorithm. The code appears in
Example 3-1
.
F
Freescale Semiconductor, Inc.
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.
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