- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄377001 > DSP56600 (飛思卡爾半導(dǎo)體(中國)有限公司) Implementing Viterbi Decoders Using the VSL Instruction on DSP Families PDF資料下載
參數(shù)資料
| 型號： | DSP56600 |
| 廠商： | 飛思卡爾半導(dǎo)體(中國)有限公司 |
| 英文描述： | Implementing Viterbi Decoders Using the VSL Instruction on DSP Families |
| 中文描述： | 維特比解碼器實(shí)現(xiàn)上使用DSP的家庭教學(xué)的VSL |
| 文件頁數(shù)： | 26/108頁 |
| 文件大?。?/td> | 726K |
| 代理商： | DSP56600 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁當(dāng)前第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁
2-12
Viterbi Decoder Implementation
For More Information On This Product,
Go to: www.freescale.com
The Viterbi Algorithm
Algorithmic Enhancements
2.4
ALGORITHMIC ENHANCEMENTS
There are a number of modifications that can be made to the algorithm in order to
improve its effectiveness as well as our ability to implement it. In our example, we count
agreements. This produces branch metrics of 0, 1, and 2. In our example butterfly,
however, the branch metrics into the state pair are all 0s and 2s. This is not entirely a
coincidence. For this code, the encoding polynomials both have taps at both extremes.
What this means is that a 1/0 at the end of the encoder will invert/not invert the encoder
output. For our trellis, this means that the pair of branches into a given state will always
have complementary branch metrics (0 and 2, or 1 and 1). By combining this observation
with one more property, we can simplify the Viterbi butterfly computation.
The additional property for this code (shown in
Figure 2-8
) is that a 1/0 at the input bit
will invert/not invert the encoder output. For our trellis, this means that the two states
of a state pair being updated will have the same branch metrics, but with their order
reversed (0 and 2 will become 2 and 0, etc.). These polynomial conditions are not true in
general but do occur quite often. To take advantage of them, we subtract 1 from every
branch metric we produce. This gives branch metric pairs of (-1,1) and (0,0).
As shown in
Figure 2-9
, each pair now has odd symmetry in the two components.
Hence, we need not compute branch metrics for both branches in an update. Instead, we
can find just the uppermost branch metric, and add it as usual for the upper branch.
Next, subtract rather than add it to do the lower branch processing. To process the lower
state update, we subtract the branch metric for the upper path and add to update the
lower path. The total path metrics change, but their relative values do not. Since we are
only looking for the path with the maximum path metric, the results are the same.
F
Freescale Semiconductor, Inc.
n
.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| DSP56852E | 16-bit Digital Signal Controllers |
| DSP56852VFE | 16-bit Digital Signal Controllers |
| DSP56853E | 16-bit Digital Signal Controllers |
| DSP56853FG120 | 16-bit Digital Signal Controllers |
| DSP56853FGE | 16-bit Digital Signal Controllers |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DSP56600AD | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:INTERGRATED CELLULAR BASEBAND PROCESSOR DEVELOPMENT IC |
| DSP56600FM | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:16-BIT DIGITAL SIGNAL PROCESSOR |
| DSP56602 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:16-Bit Digital Signal Processor User manual |
| DSP56602AD | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:16-Bit Digital Signal Processor User manual |
| DSP56602DS | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:DSP56602 16-Bit Digital Signal Processor Datasheet |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。