參數(shù)資料
型號(hào)： DSP56600
廠商： 飛思卡爾半導(dǎo)體(中國(guó))有限公司
英文描述： Implementing Viterbi Decoders Using the VSL Instruction on DSP Families
中文描述： 維特比解碼器實(shí)現(xiàn)上使用DSP的家庭教學(xué)的VSL
文件頁(yè)數(shù)： 38/108頁(yè)
文件大?。?/td> 726K
代理商： DSP56600
3-10
Viterbi Decoder Implementation
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Go to: www.freescale.com
Expanding the Viterbi Algorithm
Creating the Branch Metrics
The FindMetrics macro is for the most part straightforward. We begin by loading the
decoder input data to compute the branch metrics. Next, load the scaling factor, and
multiply to obtain the partial branch metric with one of the inputs. The next line
initializes address register r2 as a pointer to the table location used by state 3, where the
branch metrics are to be stored. We then finish the computation of the branch metric for
a branch with encoder output 00, followed by the metric for 01. With these two metrics,
we begin to load the branch metric table.
We can load the branch metric table in any order. To minimize the number of cycles
needed, we apply a few constraints. First, it is easier if we load the table in some
consistent manner such as using a constant address offset each time. Second, it is
convenient if we end up at the address used by state 0, because then we are initialized
for the butterfly state update. Also, we must finish generating the metric values for 11
and 10. It is most efficient if we can do this in parallel with the moves to load the branch
metric table.
The easiest way to store the branch metrics might be to start at state 15 and count down.
If we do this, it turns out that a stall is unavoidable: we cannot generate all of the
required branch metric values in time to use them with this ordering. Other loading
orders are easy to obtain by using an address register increment that is relatively prime
to the table length (and using a modulo addressing mode to wrap around). For our
table length, any odd number increment will ensure that we cover the entire table with
constant increments. Our first candidate is 3. If we start at state 3, and increment by 3s,
we will cover the entire table and end up at the address for state 0. These first three
branch metric values are associated with recreated encoder outputs of 00, 01 and 00.
Because the repeat of 00 gives us time to generate the extra branch metric values with
no stall, we use increments of 3.
We begin by writing the branch metric for state 3. At the same time, we negate A to
compute the metric for branches with encoder output 11, saving the metric for 00 in x1.
For the next write, we negate B to compute the metric for 10, saving the metric for 01 in
x0. We write to the branch metric table at the same time.
What follows are writes to the branch metric table. Using modulo addressing, we
increment the address by 3s until the entire table is filled. We write the branch metrics
determined by the encoder polynomials as they appear in
Table 3-1
.
Finally, note that this code has been constructed so that the address register r2 points to
the beginning of the branch metric table at the end of this routine. Because of this, the
butterfly loop is automatically initialized to load branch metrics by the end of this
routine.
F
Freescale Semiconductor, Inc.
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.
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